Abstract: Serial data transmission for dynamic random access memory (DRAM) interfaces is disclosed. Instead of the parallel data transmission that gives rise to skew concerns, exemplary aspects of the present disclosure transmit the bits of a word serially over a single lane of the bus. Because the bus is a high speed bus, even though the bits come in one after another (i.e., serially), the time between arrival of the first bit and arrival of the last bit of the word is still relatively short. Likewise, because the bits arrive serially, skew between bits becomes irrelevant. The bits are aggregated within a given amount of time and loaded into the memory array.

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

Abstract: Some features pertain to an integrated device that includes a first package, a set of interconnects, and a second package. The first package includes a first substrate comprising a first surface and a second surface. The first package includes a redistribution portion comprising a redistribution layer. The first package includes a first die coupled to the first surface of the first substrate. The set of interconnects is coupled to the redistribution portion of the first package. The second package is coupled to the first package through the set of interconnects. The second package includes a second substrate comprising a first surface and a second surface; and a second die coupled to the first surface of the second substrate, where the second die is electrically coupled to the first die through the second substrate of the second package, the set of interconnects, and the redistribution portion of the first package.

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.

Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.

Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

Abstract: A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication.

Abstract: A computer based trading system implies spread markets from multiple real or implied spread markets. In particular, one aspect of the invention permits implication of a spread market from a combination of inter-commodity and inter-calendar spread orders. Furthermore, another aspect of the invention allows use of nontradeable implied or bridge markets to combine with other implied or real markets to create further tradeable implied markets. The method described herein thereby permits the creation of all implied markets that are inherent in the combination of futures, calendar spread and inter-commodity spread real orders.

Abstract: Methods and apparatus are present for determining position of a rover from observations of GNSS signals. Observations of GNSS signals are obtained at a rover location, and observations of the GNSS signals are obtained at a plurality of reference stations, each reference station defining a respective baseline between the rover location and a reference station location. For each reference station, a respective differentially-corrected rover position is determined, wherein at least one of the differentially-corrected rover positions is based on one of (i) a multiple-frequency ionosphere-free observable combination, (ii) a multiple-frequency code-phase observable combination, and (iii) a single-frequency carrier-phase and code-plus-carrier-phase combination. A weighted combination of the differentially-corrected rover positions is prepared.

Abstract: A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.

Abstract: A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication.

Abstract: A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication.

Abstract: The use of an enzyme preparation comprising type C feruloyl esterase or type D feruloyl esterase in the manufacture of biofuels from plant cell wall materials. A method for manufacturing biofuels from plant cell wall materials by converting lignocellulosic materials in said plant cell walls to sugars suitable for use as a fermentation feedstock, which method comprises (i) contacting said plant cell wall material with an enzyme preparation comprising type C feruloyl esterase or type D feruloyl esterase and plant cell wall degrading enzymes and (ii) separating any soluble sugars therefrom for bioconversion to biofuel. A slurry prepared by converting lignocellulosic materials in plant cell walls to sugars using an enzyme preparation comprising type C feruloyl esterase or type D feruloyl esterase, and optionally plant cell-wall degrading enzymes.

Abstract: A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.

Abstract: A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.

Abstract: The present invention relates of a method of producing an enzymatic digest of proteinaceous material which can improve the palatability and health value of foodstuffs to which it is added. In particular but not exclusively, the invention involves a method where bioactive compounds are released to increase the health value of the product.

Abstract: Methods and apparatus for processing of data from GNSS receivers are presented. A post-processing engine and a post-processed accuracy predictor are described. The post-processing engine provides high accuracy GNSS (GPS) position determination with short occupation time for GIS applications. The post-processed accuracy predictor calculates during data collection an estimate of the accuracy likely to be achieved after post-processing. This helps to optimize productivity when collecting GNSS data for which post-processed accuracy is important. The predictor examines the quality of carrier measurements and estimates how well the post-processed float solution will converge in the time since carrier lock was obtained.