Patents by Inventor Ian Yang

Ian Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12751074
    Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer. The various widths are measured in a direction of a semiconductor body between the first source or drain region and the first gate structure.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: September 29, 2026
    Assignee: INTEL CORPORATION
    Inventors: Chang Wan Han, Biswajeet Guha, Vivek Thirtha, William Hsu, Ian Yang, Oleg Golonzka, Kevin J. Fischer, Suman Dasgupta, Sameerah Desnavi, Deepak Sridhar
  • Publication number: 20250311322
    Abstract: Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having a stack of nanoribbons (i.e., semiconductor structures) with thicknesses that are tuned to vary across the stack. The nanoribbon source-to-drain lengths are from a source interface to a drain interface with source and drain structures, respectively, and the thickness is orthogonal to the source-to-drain lengths in alignment with the vertical stacking of the nanoribbons. The nanoribbons have differing thicknesses across the stack of nanoribbons of the field effect transistor.
    Type: Application
    Filed: March 29, 2024
    Publication date: October 2, 2025
    Applicant: Intel Corporation
    Inventors: Michael Babb, Christopher P. Auth, Glenn Glass, Vivek Thirtha, Chen-Yi Su, William Hsu, Kawser Ahmed, Chung-Hsun Lin, Kelsey Jorgensen, Rodolfo Torres, Ian Yang
  • Publication number: 20240071831
    Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: INTEL CORPORATION
    Inventors: Chang Wan Han, Biswajeet Guha, Vivek Thirtha, William Hsu, Ian Yang, Oleg Golonzka, Kevin J. Fischer, Suman Dasgupta, Sameerah Desnavi, Deepak Sridhar