Patents by Inventor Ian Young

Ian Young has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210373991
    Abstract: Methods, apparatus, and processor-readable storage media for automated alert augmentation for deployments of software-defined storage are provided herein. An example computer-implemented method includes obtaining an alert from at least one software-defined storage device; determining one or more items of additional information pertaining to one or more of the alert and the at least one software-defined storage device; augmenting the alert based at least in part on the one or more determined items of additional information; generating a modified version of the augmented alert by incorporating, into the augmented alert, dependency information pertaining to the at least one software-defined storage device and one or more additional software-defined storage devices; and performing one or more automated actions based at least in part on the modified version of the augmented alert.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Sean R. Gallacher, Trevor H. Dawe, Eric Young, Ian D. Bibby
  • Patent number: 11171145
    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Sou-Chi Chang, Uygar Avci, Daniel H. Morris, Seiyon Kim, Ashish V. Penumatcha, Ian A. Young
  • Publication number: 20210343856
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.
    Type: Application
    Filed: June 1, 2021
    Publication date: November 4, 2021
    Applicant: Intel Corporation
    Inventors: Nazila Haratipour, Sou-Chi Chang, Chia-Ching Lin, Jack Kavalieros, Uygar Avci, Ian Young
  • Patent number: 11158429
    Abstract: The present invention provides an integrated health care surveillance and monitoring system that provides real-time sampling, modeling, analysis, and recommended interventions. The system can be used to monitor infectious and chronic diseases. When faced with outbreak of an infectious disease agent, e.g., influenza virus, the system can identify active cases through pro-active sampling in high risk locations, such as schools or crowded commercial areas. The system can notify appropriate entities, e.g., local, regional and national governments, when an event is detected, thereby allowing for proactive management of a possible outbreak. The system also predicts the best response for deployment of scarce resources.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: October 26, 2021
    Assignee: Labrador Diagnostics LLC
    Inventors: Elizabeth A. Holmes, Ian Gibbons, Daniel Young, Seth G. Michelson
  • Patent number: 11151046
    Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Amrita Mathuriya, Sasikanth Manipatruni, Victor Lee, Huseyin Sumbul, Gregory Chen, Raghavan Kumar, Phil Knag, Ram Krishnamurthy, Ian Young, Abhishek Sharma
  • Patent number: 11139389
    Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A Young
  • Patent number: 11138499
    Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Sharma, Jack T. Kavalieros, Ian A. Young, Sasikanth Manipatruni, Ram Krishnamurthy, Uygar Avci, Gregory K. Chen, Amrita Mathuriya, Raghavan Kumar, Phil Knag, Huseyin Ekin Sumbul, Nazila Haratipour, Van H. Le
  • Patent number: 11139084
    Abstract: The present invention provides an integrated health care surveillance and monitoring system that provides real-time sampling, modeling, analysis, and recommended interventions. The system can be used to monitor infectious and chronic diseases. When faced with outbreak of an infectious disease agent, e.g., influenza virus, the system can identify active cases through pro-active sampling in high risk locations, such as schools or crowded commercial areas. The system can notify appropriate entities, e.g., local, regional and national governments, when an event is detected, thereby allowing for proactive management of a possible outbreak. The system also predicts the best response for deployment of scarce resources.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: October 5, 2021
    Assignee: Labrador Diagnostics LLC
    Inventors: Elizabeth A. Holmes, Ian Gibbons, Daniel Young, Seth G. Michelson
  • Publication number: 20210298626
    Abstract: A method of processing ECG data includes generating a first feature set with a trained neural network using ECG data and processing a patient's ECG data using a criteria-based algorithm to generate a second feature set. The patient's ECG data is then clustered into a number of clusters based on the first feature set and the second feature set to generate clustered ECG data. The clustered ECG data is presented to a user via a user interface, and user input is received from the user via the user interface regarding the clustered ECG data. A feature vector is defined based on the user input and the feature vector is applied to at least a portion of the patient's ECG data to generate revised clustered ECG data. The revised clustered ECG data is then presented to the user via the user interface.
    Type: Application
    Filed: March 30, 2020
    Publication date: September 30, 2021
    Applicant: GE Precision Healthcare LLC
    Inventors: Long Yu, Brian J. Young, Joel Qiuzhen Xue, Gordan Ian Rowlandson
  • Publication number: 20210305398
    Abstract: A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Applicant: Intel Corporation
    Inventors: Sou-Chi Chang, Chia-Ching Lin, Nazila Haratipour, Tanay Gosavi, I-Cheng Tung, Seung Hoon Sung, Ian Young, Jack Kavalieros, Uygar Avci, Ashish Verma Penumatcha
  • Patent number: 11127785
    Abstract: A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
  • Patent number: 11114144
    Abstract: An apparatus is provided which comprises: a first paramagnet; a stack of layers, a portion of which is adjacent to the first paramagnet, wherein the stack of layers is to provide an inverse Rashba-Edelstein effect; a second paramagnet; a magnetoelectric layer adjacent to the second paramagnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
  • Patent number: 11107908
    Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Anurag Chaudhry, Dmitri E. Nikonov, Jasmeet S. Chawla, Christopher J. Wiegand, Kanwaljit Singh, Uygar E. Avci, Ian A. Young
  • Patent number: 11069609
    Abstract: Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Jasmeet S. Chawla, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young, Robert L. Bristol
  • Patent number: 11061646
    Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Huseyin Ekin Sumbul, Phil Knag, Gregory K. Chen, Raghavan Kumar, Abhishek Sharma, Sasikanth Manipatruni, Amrita Mathuriya, Ram Krishnamurthy, Ian A. Young
  • Patent number: 11062752
    Abstract: A perpendicular spin orbit torque memory device includes a first electrode having tungsten and at least one of nitrogen or oxygen and a material layer stack on a portion of the first electrode. The material layer stack includes a free magnet, a fixed magnet above the first magnet, a tunnel barrier between the free magnet and the fixed magnet and a second electrode coupled with the fixed magnet.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Tofizur Rahman, James Pellegren, Angeline Smith, Christopher Wiegand, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Benjamin Buford, Ian Young
  • Patent number: 11063131
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Nazila Haratipour, Sou-Chi Chang, Chia-Ching Lin, Jack Kavalieros, Uygar Avci, Ian Young
  • Patent number: 11056593
    Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Uygar E. Avci, Christopher J. Wiegand, Anurag Chaudhry, Jasmeet S. Chawla, Ian A Young
  • Patent number: 11048434
    Abstract: A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Raghavan Kumar, Phil Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Sasikanth Manipatruni, Amrita Mathuriya, Abhishek Sharma, Ram Krishnamurthy, Ian A. Young
  • Patent number: D934846
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: November 2, 2021
    Assignee: Charter Communications Operating, LLC
    Inventors: Chelsea Young, Ian Ruppert, Ethan Miller