Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

Abstract: Embodiments of the present disclosure are directed toward probabilistic in-memory computing configurations and arrangements, and configurations of probabilistic bit devices (p-bits) for probabilistic in-memory computing. concept with emerging. A probabilistic in-memory computing device includes an array of p-bits, where each p-bit is disposed at or near horizontal and vertical wires. Each p-bit is a time-varying resistor that has a time-varying resistance, which follows a desired probability distribution. The time-varying resistance of each p-bit represents a weight in a weight matrix of a stochastic neural network. During operation, an input voltage is applied to the horizontal wires to control the current through each p-bit. The currents are accumulated in the vertical wires thereby performing respective multiply-and-accumulative (MAC) operations. Other embodiments may be described and/or claimed.

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode. An insulator is over the first electrode. The insulator includes a first layer, and a second layer over the first layer. The first layer has a leakage current that is less than a leakage current of the second layer. The second layer has a dielectric constant that is greater than a dielectric constant of the first layer. A second electrode is over the insulator.

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.

Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack.

Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

Abstract: Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip.

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

Abstract: Described herein are capacitor devices formed using perovskite insulators. In one example, a perovskite templating material is formed over an electrode, and a perovskite insulator layer is grown over the templating material. The templating material improves the crystal structure and electrical properties in the perovskite insulator layer. One or both electrodes may be ruthenium. In another example, a perovskite insulator layer is formed between two layers of indium tin oxide (ITO), with the ITO layers forming the capacitor electrodes.

Abstract: Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.

Abstract: A time alignment method for a differential protection device, the differential protection device and a differential protection system are disclosed. The time alignment method includes obtaining a plurality of current sampled values and a count value of each current sampled values; resampling the plurality of current sampled values with sampling frequency of J points/cycle to obtain a plurality of current resampled values; and performing Fourier transform on the plurality of current resampled values to obtain a plurality of temporally arranged current Fourier values, the plurality of current Fourier values includes a reference current Fourier value corresponding to the sampling moment of the current sampled value whose count value is the first value in the plurality of current sampled values, and the reference current Fourier value is determined based on the reference current resampled value and the J?1 current resampled values that temporally arranged before the reference current resampled value.

Abstract: Provided are a data alignment method, a differential protector, and a differential protection system. The data alignment method comprises: obtaining first sampled current data from a first sampling device; receiving a second message from a second differential protector, the second message comprising second sampled current data and its sampling time stamp, first time information of the second differential protector related to a difference in time of reception from receipt of the first message to a second time node, and second time information of the second differential protector related to a second transmission processing delay from the second time node to transmission of the second message; when time synchronization is maintained, calculating and storing a time calculation deviation between a third time node and a first calculated value of the second time node; when time synchronization is lost, determining the third time node according to the stored time calculation deviation.

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a FinFET transistor on the substrate. The FinFET transistor includes a fin structure having a channel area, a source area, and a drain area. The FinFET transistor further includes a gate dielectric area between spacers above the channel area of the fin structure and below a top surface of the spacers; spacers above the fin structure and around the gate dielectric area; and a metal gate conformally covering and in direct contact with sidewalls of the spacers. The gate dielectric area has a curved surface. The metal gate is in direct contact with the curved surface of the gate dielectric area. Other embodiments may be described and/or claimed.