Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

Abstract: Provided are a data alignment method, a differential protector, and a differential protection system. The data alignment method comprises: obtaining first sampled current data from a first sampling device; receiving a second message from a second differential protector, the second message comprising second sampled current data and its sampling time stamp, first time information of the second differential protector related to a difference in time of reception from receipt of the first message to a second time node, and second time information of the second differential protector related to a second transmission processing delay from the second time node to transmission of the second message; when time synchronization is maintained, calculating and storing a time calculation deviation between a third time node and a first calculated value of the second time node; when time synchronization is lost, determining the third time node according to the stored time calculation deviation.

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.

Abstract: A neural network scheme is described that uses unsupervised learning in oscillator neural networks. Training occurs by varying the weights in proportion to the output from a frequency detector. Inputs and initial weights are split into plurality of inputs and plurality of weights. These split inputs and weights can be analog or digital. Oscillators generate signals having frequencies that represent difference in inputs, initial weights, and adjusted factors. Frequency detectors are used to compare the oscillator frequencies with a synchronized frequency of all oscillators. The output of the frequency detectors are used to generate the adjusted factors, and in turn generate trained weights.

Abstract: Systems and methods for precision writing of weight values to a memory capable of storing multiple levels in each cell are disclosed. Embodiments include logic to compare an electrical parameter read from a memory cell with a base reference and an interval reference, and stop writing once the electrical parameter is between the base reference and the base plus the interval reference. The interval may be determined using a greater number of levels than the number of stored levels, to prevent possible overlap of read values of the electrical parameter due to memory device variations.

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

Abstract: Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.

Abstract: A time alignment method for a differential protection device, the differential protection device and a differential protection system are disclosed. The time alignment method includes obtaining a plurality of current sampled values and a count value of each current sampled values; resampling the plurality of current sampled values with sampling frequency of J points/cycle to obtain a plurality of current resampled values; and performing Fourier transform on the plurality of current resampled values to obtain a plurality of temporally arranged current Fourier values, the plurality of current Fourier values includes a reference current Fourier value corresponding to the sampling moment of the current sampled value whose count value is the first value in the plurality of current sampled values, and the reference current Fourier value is determined based on the reference current resampled value and the J?1 current resampled values that temporally arranged before the reference current resampled value.

Abstract: Provided are a data alignment method, a differential protector, and a differential protection system. The data alignment method comprises: obtaining first sampled current data from a first sampling device; receiving a second message from a second differential protector, the second message comprising second sampled current data and its sampling time stamp, first time information of the second differential protector related to a difference in time of reception from receipt of the first message to a second time node, and second time information of the second differential protector related to a second transmission processing delay from the second time node to transmission of the second message; when time synchronization is maintained, calculating and storing a time calculation deviation between a third time node and a first calculated value of the second time node; when time synchronization is lost, determining the third time node according to the stored time calculation deviation.

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

Abstract: An apparatus is provided which comprises: a bit-line; a first word-line; a second word-line; and a source-line; a magnetic junction comprising a free magnet; an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the free magnet of the magnetic junction; and a first device (e.g., a selector device) coupled at one end of the interconnect and to the second word-line; and a second device coupled to the magnetic junction, the first word-line and the source-line.

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.

Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.

Abstract: Embodiments disclosed herein include transistor devices with complex oxide interfaces and methods of forming such devices. In an embodiment, the transistor device may comprise a substrate, and a fin extending up from the substrate. In an embodiment, a first oxide is formed over sidewall surfaces of the fin, and a second oxide is formed over the first oxide. In an embodiment, the first oxide and the second oxide are perovskite oxides with the general formula of ABO3.