Abstract: A convolution layer processor for a neural network accelerator includes a memory access module to access elements of an input feature map having a first array of pixels and a plurality of convolution modules. Each convolution module receives an element of the input feature map and performs a convolution operation on the received element of the input feature map with a convolution kernel having a second array of pixels to provide a corresponding element of an output feature map. The memory access module includes a DMA requester to request elements of the input feature map, a data buffer to provide the requested elements to each of the plurality of convolution modules, and a pad supervisor module to provide to the data buffer, for each element requested by the DMA requester, padding pixels of the input feature map when the requested element extends beyond a boundary of the input feature map.

Abstract: A memory address generator for generating an address of a location in a memory includes a first address input for receiving a first address having a location in the memory being accessed during a first memory access cycle, and a next address output configured to output a next address comprising a location in the memory to be accessed during a subsequent memory access cycle based on the current address and a memory address increment value The address increment unit includes a counter arrangement and a selector arrangement, wherein each counter of the counter arrangement is configured to provide an output signal at the output indicative of a maximum value being reached and the selector arrangement is configured to provide a candidate memory address increment value based on the output of the counter arrangement as the memory address increment value output by the address increment unit.

Abstract: A memory address generator for generating an address of a location in a memory includes a first address input for receiving a first address having a location in the memory being accessed during a first memory access cycle, and a next address output configured to output a next address comprising a location in the memory to be accessed during a subsequent memory access cycle based on the current address and a memory address increment value. The address increment unit includes a counter arrangement and a selector arrangement, wherein each counter of the counter arrangement is configured to provide an output signal at the output indicative of a maximum value being reached and the selector arrangement is configured to provide a candidate memory address increment value based on the output of the counter arrangement as the memory address increment value output by the address increment unit.