Abstract: In the transfer of information packets in a network the information (7) is transmitted by the sending terminal station (1A) provided with a destination address field (9). The destination address field (9) comprises references or codes of the input lines/output lines or connection lines which are to be used when the information packet is retransmitted from nodes (5) in the network. In the corresponding way each information packet is in a node provided with address information in a return address field (11) indicating the connection line or combined input line/output line on which the information packet arrived to the node (5). Thereby the information packet, in a simple way, is provided with a return address and it may be utilized by the receiving terminal station (1.sub.B) for instance for the transfer of a receipt message.

Abstract: The invention relates to a telecommunication system in which alternatingly circuit-switeched and packet-switched information is transmitted in time-divided form between transmitter and receiver equipments.A system is described for multiplexing telephony channels with static and dynamic capacity. A static channel occupies a time slot in a fixed frame structure. The dynamic channels utilize idle time slots. A status bit per time slot states whether the time slot is occupied or not. According to the invention, equipment for transmitting circuit-switched information is combined with equipment for transmitting packet-switched information, such that a hybrid system is obtained which, under the control of a status bit, alternatingly transfers information from the respective equipment in response to the polarity of the status bit.A circuit-switching memory (CS) is continuously scanned in a multiplexer (DS1).

Abstract: An apparatus in a computer-controlled telecommunication system for carrying out load regulation with the aid of a queueing system for insuring that, in transmission of data information between a regional processor (RP) and a central processor (CP), all program levels in said central processor are guaranteed a positive share of the processor capacity. In the regional processor transmitter (RP) are included a transmitter memory (SM) and a ticket memory (BM). A regulator unit (R) is included in the central processor or receiver (CP) and comprises a plurality of regulator members (S-N), where each is utilized on a given program level and cooperates with a job buffer (JBB-JBN) associated with the program level. The regulator member (S) corresponds to the highest program level and the member (N) to the lowest. Each member, apart from the last one, contains three memory units (KB,KM,KK) in the form of counters. The last member (N) in the chain of regulator members contains only one counter (KB).