Abstract: Bee venom nanoparticles and methods of synthesizing bee venom nanoparticles are provided. The bee venom nanoparticles may be synthesized by drying bee venom, suspending the dried bee venom in a solvent to form a first bee venom solution, spraying the first bee venom solution into boiling water under ultrasonic conditions to form a bee venom solution including the bee venom nanoparticles, stirring the bee venom solution including the bee venom nanoparticles, and freeze-drying the bee venom solution. The resulting nanoparticles may be used in pharmaceutical compositions, and may be useful for their antimicrobial activities.

Abstract: Authentication devices and methods. The authentication device includes a connection component configured to establish a physical connection with a computing system configured to perform at least an authentication procedure, a housing including a screen portion to at least visually present authentication data as part of an interaction with the computing system, and a cable portion connecting the housing and the connection component, wherein the cable portion is configured to prevent stress from being imparted on the connection component at least due to handling of the housing.

Abstract: Compute engine circuitry configured to represent a spin network mapping of a graph representing a combinatorial optimization problem includes a plurality of ring oscillator cells, each of which includes a ring oscillator having an oscillator output, at least one coupling block, and a read block. Each coupling block connects the ring oscillator of the cell to the ring oscillator of one of a plurality of neighboring cells to form a coupled ring oscillator. The read block generates a state output for each coupled ring oscillator that indicates whether the coupled ring oscillator is in one of a same-phase state, in which the connected ring oscillators oscillate in phase with each other, and an opposite-phase state, in which the connected ring oscillators oscillate in an opposite phase from each other. A controller is configured to output a total energy of the mapping based on the state outputs.

Abstract: Facilitating efficient processing of transformer based models is provided herein. A low latency processing system includes a transformer having an embedding layer and a Tensor Streaming Processor (TSP) having a Matrix Multiplication module (MXM) and Vector Calculation module (VXM). The TSP is arranged to deterministically process information arranged by the embedding layer and an encoder layer with the associated self-attention mechanism, the information being further modified according to the transformer using a general matrix multiply (GEMM) mapped directly on the MXM and associated accumulator. Further, at least some set of information is processed to parallelize the execution of GEMMs across all MXM planes.

Abstract: A refrigerator appliance includes a liner positioned within a cabinet, the liner having an inner liner surface that defines a chilled chamber and an aperture that passes through the liner. A light assembly is mounted to the liner and includes a light source positioned within a light housing in the insulated space between the liner and the cabinet. A lens is mounted to the light housing and is positioned within the aperture, the lens defining an outer lens surface that sits flush with the inner liner surface and an inner lens surface defining a plurality of refractive grooves.

Abstract: The present disclosure relates generally to targeted gene editing constructs, including methods of designing a DNA-recognition moiety for modulation of gene expression in plants, DNA-recognition moieties, gene editing constructs, methods for the modulation of gene expression in plants using gene editing constructs, and plants or regenerable plant cells produced therefrom.

Abstract: An automated door assembly for a dishwasher appliance includes a door frame pivotally mounted to the cabinet. An extension arm is mounted to and extends away from the door frame at approximately 90 degrees. A motor is mounted to the cabinet and is coupled to a distal end of the extension arm by a cable. The motor is selectively rotated to wind and unwind the cable to move the door frame between the closed position and the open position. A latch assembly engages a striker mounted on the door frame to initiate the opening and closing process.

Abstract: Provided herein are a method of using thermochromic ink for blood simulation in medical training and a method of using thermochromic ink for blood simulation. A prominent application is for simulation of Extracorporeal Membrane Oxygenation (ECMO) simulation.

Abstract: The present invention relates generally to an artificial plant seed and to its use for plant propagation, in particular, for the propagation of cannabis plants.

Abstract: Compute engine circuitry configured to represent a spin network mapping of a graph representing a combinatorial optimization problem includes a plurality of ring oscillator cells, each of which includes a ring oscillator having an oscillator output, at least one coupling block, and a read block. Each coupling block connects the ring oscillator of the cell to the ring oscillator of one of a plurality of neighboring cells to form a coupled ring oscillator. The read block generates a state output for each coupled ring oscillator that indicates whether the coupled ring oscillator is in one of a same-phase state, in which the connected ring oscillators oscillate in phase with each other, and an opposite-phase state, in which the connected ring oscillators oscillate in an opposite phase from each other. A controller is configured to output a total energy of the mapping based on the state outputs.

Abstract: Modern FPGAs operate at a core voltage around 1V and therefore even small voltage fluctuations can lead to timing violations and logic errors. The Power Delivery Network (PDN) between a power supply and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. The present disclosure describes two techniques for characterization of the PDN: 1) to extract the DC resistance in the power delivery path, and 2) to identify the high impedance frequency band(s) in the PDN. An embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. A self-calibrated Carry-Chain based ADC (CC-ADC) is used for high-speed sampling of the core voltage. By modifying the PDN based on the extracted results, the voltage operating range and reliability of a crossbar application may be greatly extended.

Abstract: An automated door assembly for a dishwasher appliance includes a door frame pivotally mounted to the cabinet. An extension arm is mounted to and extends away from the door frame at approximately 90 degrees. A motor is mounted to the cabinet and is coupled to a distal end of the extension arm by a cable. The motor is selectively rotated to wind and unwind the cable to move the door frame between the closed position and the open position. A latch assembly engages a striker mounted on the door frame to initiate the opening and closing process.

Abstract: Methods and systems for operating a programmable logic fabric (16) including a dynamic parameter scaling controller (22) that tracks an operating parameter that functions at multiple operating conditions by maintaining the operating parameter while cycling through multiple operating conditions during a calibration mode using the calibration configuration for the programmable logic fabric (16). The dynamic parameter scaling controller (22) also stores one or more functional values for the operating parameter in a calibration table. The dynamic parameter scaling controller (22) also operates the programmable logic fabric (16) using a design configuration using dynamic values for the operating parameter based at least in part on the one or more operating conditions.

Abstract: In an example embodiment performance is optimized in a complex event stream (CEP) system. Information about a plurality of CEP threads is obtained. Then nearness among the plurality of CEP threads is determined, wherein nearness between a first and a second CEP thread indicates how much interaction is expected to occur between the first and second CEP thread. Based on the determined nearness, the plurality of CEP threads are organized into a plurality of CEP thread groups. Then, each of the plurality of CEP thread groups are assigned to a different processing node, with each processing node having one or more processors and a memory.

Abstract: Provided herein are a method of using thermochromic ink for blood simulation in medical training and a method of using thermochromic ink for blood simulation. A prominent application is for simulation of Extracorporeal Membrane Oxygenation (ECMO) simulation.

Abstract: Modern FPGAs operate at a core voltage around 1V and therefore even small voltage fluctuations can lead to timing violations and logic errors. The Power Delivery Network (PDN) between a power supply and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. The present disclosure describes two techniques for characterization of the PDN: 1) to extract the DC resistance in the power delivery path, and 2) to identify the high impedance frequency band(s) in the PDN. An embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. A self-calibrated Carry-Chain based ADC (CC-ADC) is used for high-speed sampling of the core voltage. By modifying the PDN based on the extracted results, the voltage operating range and reliability of a crossbar application may be greatly extended.

Abstract: Methods and systems for operating a programmable logic fabric (16) including a dynamic parameter scaling controller (22) that tracks an operating parameter that functions at multiple operating conditions by maintaining the operating parameter while cycling through multiple operating conditions during a calibration mode using the calibration configuration for the programmable logic fabric (16). The dynamic parameter scaling controller (22) also stores one or more functional values for the operating parameter in a calibration table. The dynamic parameter scaling controller (22) also operates the programmable logic fabric (16) using a design configuration using dynamic values for the operating parameter based at least in part on the one or more operating conditions.

Abstract: In an example embodiment performance is optimized in a complex event stream (CEP) system. Information about a plurality of CEP threads is obtained. Then nearness among the plurality of CEP threads is determined, wherein nearness between a first and a second CEP thread indicates how much interaction is expected to occur between the first and second CEP thread. Based on the determined nearness, the plurality of CEP threads are organized into a plurality of CEP thread groups. Then, each of the plurality of CEP thread groups are assigned to a different processing node, with each processing node having one or more processors and a memory.

Abstract: In an example embodiment, performance is optimized in a complex event stream (CEP) system. Information about a plurality of CEP threads is obtained. Then nearness among the plurality of CEP threads is determined, wherein nearness between a first and a second CEP thread indicates how much interaction is expected to occur between the first and second CEP thread. Based on the determined nearness, the plurality of CEP threads are organized into a plurality of CEP thread groups. Then, each of the plurality of CEP thread groups are assigned to a different processing node, with each processing node having one or more processors and a memory.

Abstract: Methods and systems for operating a programmable logic fabric including a dynamic parameter scaling controller that tracks an operating parameter that functions at multiple operating conditions by maintaining the operating parameter while cycling through a multiple operating conditions during a calibration mode using the calibration configuration for the programmable logic fabric. The dynamic parameter scaling controller also stores one or more functional values for the operating parameter in a calibration table. The dynamic parameter scaling controller also operates the programmable logic fabric using a design configuration using dynamic values for the operating parameter based at least in part on the one or more operating conditions.