Patents by Inventor Ibrahim Avci

Ibrahim Avci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12361509
    Abstract: In an example, a multi-level data structure is defined including fine grid (FG) and coarse levels. The FG level is configured to store FG data of FG points. The coarse level is configured to store, for a respective chunk of FG points, compressed FG data and/or a pointer to corresponding FG data of the respective chunk. First chunks are identified by a graphics processing unit (GPU) and include each chunk of the FG points including one or more of: (i) that includes a FG point in a level set layer L0 (LSL0), and (ii) that neighbors a chunk that includes the FG point in the LSL0. Memory of the GPU is allocated for the first chunks that have respective compressed FG data to be decompressed. Level set values of the FG points in the LSL0 stored in the FG level in the allocated memory are updated by the GPU.
    Type: Grant
    Filed: August 21, 2023
    Date of Patent: July 15, 2025
    Assignee: Synopsys, Inc.
    Inventors: Zhiqiang Tan, Ibrahim Avci, Luis Villablanca
  • Patent number: 10776552
    Abstract: An integrated circuit design tool for modeling resistance of an interconnect specifies a structure of the interconnect in a data structure in memory in or accessible by the computer system using 3D coordinate system. For each of a plurality of volume elements in the specified structure, the tool specifies a location and one of first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as a function of resistivity of volume elements within a neighborhood of the volume element and a specified transition region length ?.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: September 15, 2020
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Ibrahim Avci, Shuqing Li, Philippe Roussel, Ivan Ciofi
  • Publication number: 20180157783
    Abstract: An integrated circuit design tool for modeling resistance of an interconnect specifies a structure of the interconnect in a data structure in memory in or accessible by the computer system using 3D coordinate system. For each of a plurality of volume elements in the specified structure, the tool specifies a location and one of first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as a function of resistivity of volume elements within a neighborhood of the volume element and a specified transition region length ?.
    Type: Application
    Filed: November 27, 2017
    Publication date: June 7, 2018
    Applicant: Synopsys, Inc.
    Inventors: Victor Moroz, Ibrahim Avci, Shuqing Li, Philippe Roussel, Ivan Ciofi