Abstract: Disclosed embodiments relate to an indirect memory fetch (IMF) unit. In one example, an apparatus includes circuitry to fetch and decode an instruction specifying a sparse operand array including N operands, and an index array including N contiguously-addressed indices. The apparatus further includes a processing engine associated with an IMF unit to respond to the decoded instruction by initializing the IMF unit to fetch the N operands in order, probing the IMF unit to determine that a fetched operand is ready to retrieve, retrieving the fetched operand from the IMF unit, and repeating the probing and retrieving until all N operands have been retrieved. The IMF unit, independent of the processing engine, is to fetch the N contiguously-addressed indices from the index array, use the N fetched indices to calculate memory addresses for the N operands, and issue a plurality of read requests to fetch the N operands in order.

Abstract: An example processor that includes a register, a cache, a processor core, and a programmable logic circuit. The register may store a first prefetch value indicating a first amount of time to prefetch data from a memory prior to an execution of a subsequent instruction that uses the data. The processor core may be coupled to the cache and the register. The processor core may execute a prefetch instruction to access the data from the memory, store a copy of the data in the cache, and execute the subsequent instruction. The programmable logic circuit may be coupled to the processor core. The programmable logic circuit may determine whether the first amount of time is insufficient to prefetch the data for the execution of the subsequent instruction and change the first prefetch value to a second prefetch value when the first amount of time is insufficient.

Abstract: Embodiment of this disclosure provides a mechanism to store cache lines in dedicated cache of an idle core. In one embodiment, a multi-core processor comprising a first core, a second core, a first cache, a second cache, a third cache, and a cache controller unit is provided. The cache controller is operatively coupled to at least the first cache, the second cache, and the third cache. The cache controller is to evict a first line from the first cache, wherein the first core is in an active state. Responsive to the evicting of the first line, the first line is stored in the third cache. Responsive to storing the first line, a second line is evicted from the third cache. Responsive to evicting the second line, the second line is stored in the second cache when the second core is in an idle state.

Abstract: Embodiments of apparatuses, methods, and systems for independent tuning of multiple hardware prefetchers are described. In an embodiment, an apparatus includes a processor core, a cache memory, a hardware prefetcher, and a prefetch tuner. The hardware prefetcher is to prefetch data for the processor core from a system memory to the cache memory. The prefetch tuner is to adjust a prefetch rate of the hardware prefetcher based on a fraction of late prefetches. The prefetch tuner includes a late prefetch counter to count a number of late prefetches for the hardware prefetcher, a prefetch counter to count a number of prefetches for the hardware prefetcher, and a late prefetch calculator to calculate the fraction of late prefetches based on the number of late prefetches and the number of prefetches.

Abstract: Embodiments of apparatuses, methods, and systems for independent tuning of multiple hardware prefetchers are described. In an embodiment, an apparatus includes a processor core, a cache memory, a hardware prefetcher, and a prefetch tuner. The hardware prefetcher is to prefetch data for the processor core from a system memory to the cache memory. The prefetch tuner is to adjust a prefetch rate of the hardware prefetcher based on a fraction of late prefetches. The prefetch tuner includes a late prefetch counter to count a number of late prefetches for the hardware prefetcher, a prefetch counter to count a number of prefetches for the hardware prefetcher, and a late prefetch calculator to calculate the fraction of late prefetches based on the number of late prefetches and the number of prefetches.

Abstract: Methods, apparatus, systems and articles of manufacture to build a storage architecture for graph data are disclosed herein. Disclosed example apparatus include a neighbor identifier to identify respective sets of neighboring vertices of a graph. The neighboring vertices included in the respective sets are adjacent to respective ones of a plurality of vertices of the graph and respective sets of neighboring vertices are represented as respective lists of neighboring vertex identifiers. The apparatus also includes an element creator to create, in a cache memory, an array of elements that are unpopulated. The array elements have lengths equal to a length of a cache line. In addition, the apparatus includes an element populater to populate the elements with neighboring vertex identifiers. Each of the elements store neighboring vertex identifiers of respective ones of the list of neighboring vertex identifiers.

Abstract: Technologies for processor architecture simulation with machine learning include a computing device that simulates performance of a processor executing training programs with a simulation model. The computing device captures ground truth performance statistics of the processor executing the training programs, for example using a cycle-accurate simulator. The computing device collects training simulation statistics from the simulation model and trains an error model with the training simulation statistics as feature vector and with the ground truth performance statistics. The computing device may simulate performance of the processor executing a test program, capture test simulation statistic from the simulation model, and predict a predicted error of the simulation model using the error model with the test simulation statistics as feature vector. The computing device may adjust output of the simulation model or adapt execution of the simulation model based on the predicted error.

Abstract: An example processor that includes a register, a cache, a processor core, and a programmable logic circuit. The register may store a first prefetch value indicating a first amount of time to prefetch data from a memory prior to an execution of a subsequent instruction that uses the data. The processor core may be coupled to the cache and the register. The processor core may execute a prefetch instruction to access the data from the memory, store a copy of the data in the cache, and execute the subsequent instruction. The programmable logic circuit may be coupled to the processor core. The programmable logic circuit may determine whether the first amount of time is insufficient to prefetch the data for the execution of the subsequent instruction and change the first prefetch value to a second prefetch value when the first amount of time is insufficient.

Abstract: A method for preforming memory prefetching is disclosed. A stream length histogram (SLH) is initially generated based on a stream of Read and Write requests intended for a system memory. A determination is then made whether or not to issue a prefetch command after a Read request based on information within the generated SLH. In a determination that a prefetch command should be issued, prefetch command to be sent to the system memory is issued along with other commands.

Abstract: A method for preforming memory prefetching and scheduling prefetch commands inside the memory controller is disclosed. A set of prefetch commands is generated based on a stream of Read requests intended for a system memory, and the prefetch commands are stored in a low priority queue (LPQ). A set of regular commands is generated based on a stream of Read and Write requests intended for the system memory, and the regular commands are stored in a centralized arbiter queue. One of the prefetch commands is issued from the LPQ depending on the status of the other queues in the memory controller.

Abstract: A memory controller uses a power- and performance-aware scheduler which reorders memory commands based on power priorities. Selected memory ranks of the memory device are then powered down based on rank localities of the reordered commands. The highest power priority may be given to memory commands having the same rank as the last command sent to the memory device. Any memory commands having the same power priority can be further sorted based on one or more performance criteria such as an expected latency of the memory commands and an expected ratio of read and write memory commands. To optimize the power-down function, the power-down command is only sent when the selected memory rank is currently idle, the selected memory rank is not already powered down, none of the reordered memory commands correspond to the selected rank, and a currently pending memory command cannot be issued in the current clock cycle.

Abstract: A memory controller uses a throttling mechanism which estimates a throttling delay for achieving a target power consumption, and periodically blocks all memory commands for a number of clock cycles corresponding to the throttling delay. Idle memory ranks of the memory device are powered down while the memory commands are blocked. A regression model bases the throttling delay on a plurality of operating factors and a plurality of regression coefficients for the operating factors. In the illustrative implementation the operating factors include power consumption, a current number of bank conflicts, a current number of read commands, and a current number of write commands. Different sets of regression coefficients can be programmably stored for use with different system configurations.

Abstract: A method for preforming memory prefetching is disclosed. A stream length histogram (SLH) is initially generated based on a stream of Read and Write requests intended for a system memory. A determination is then made whether or not to issue a prefetch command after a Read request based on information within the generated SLH. In a determination that a prefetch command should be issued, prefetch command to be sent to the system memory is issued along with other commands.

Abstract: A method for preforming memory prefetching and scheduling prefetch commands inside the memory controller is disclosed. A set of prefetch commands is generated based on a stream of Read requests intended for a system memory, and the prefetch commands are stored in a low priority queue (LPQ). A set of regular commands is generated based on a stream of Read and Write requests intended for the system memory, and the regular commands are stored in a centralized arbiter queue. One of the prefetch commands is issued from the LPQ depending on the status of the other queues in the memory controller.

Abstract: A memory controller uses a power- and performance-aware scheduler which reorders memory commands based on power priorities. Selected memory ranks of the memory device are then powered down based on rank localities of the reordered commands. The highest power priority may be given to memory commands having the same rank as the last command sent to the memory device. Any memory commands having the same power priority can be further sorted based on one or more performance criteria such as an expected latency of the memory commands and an expected ratio of read and write memory commands. To optimize the power-down function, the power-down command is only sent when the selected memory rank is currently idle, the selected memory rank is not already powered down, none of the reordered memory commands correspond to the selected rank, and a currently pending memory command cannot be issued in the current clock cycle.

Abstract: A memory controller uses a throttling mechanism which estimates a throttling delay for achieving a target power consumption, and periodically blocks all memory commands for a number of clock cycles corresponding to the throttling delay. Idle memory ranks of the memory device are powered down while the memory commands are blocked. A regression model bases the throttling delay on a plurality of operating factors and a plurality of regression coefficients for the operating factors. In the illustrative implementation the operating factors include power consumption, a current number of bank conflicts, a current number of read commands, and a current number of write commands. Different sets of regression coefficients can be programmably stored for use with different system configurations.

Abstract: A method, system and computer program product for creating and dynamically selecting an arbiter design within a data processing system on the basis of command history is disclosed. The method includes selecting a first arbiter for current use in arbitrating between requestors for a resource. During operation of said data processing system, an arbiter selection unit detects requests for the resource and selects a second arbiter in response to the detected requests for the resource.

Abstract: A method, system and computer program product for creating and dynamically selecting an arbiter design within a data processing system on the basis of command history is disclosed. The method includes selecting a first arbiter for current use in arbitrating between requestors for a resource. During operation of said data processing system, an arbiter selection unit detects requests for the resource and selects a second arbiter in response to the detected requests for the resource.