Abstract: Disclosed are techniques for chip-to-chip (C2C) serial communications, such as communications between chiplets on a multi-chip package. In some aspects, a method of on-die monitoring of C2C links comprises detecting a change of the C2C link from a first link state to a second link state and storing link state change information in an on-die first-in, first-out (FIFO) buffer. The link state change information indicates the first link state, the duration of time the C2C link was in the first link state, and the speed of the C2C link in the first link state. Upon detecting a request for link state change information, link state change information is retrieved from the FIFO buffer and transmitted serially to an output pin of the die, such as a general purpose input/output (GPIO) pin.

Abstract: Disclosed are techniques for chip-to-chip (C2C) serial communications, such as communications between chiplets on a multi-chip package. In some aspects, a method of on-die monitoring of C2C links comprises detecting a change of the C2C link from a first link state to a second link state and storing link state change information in an on-die first-in, first-out (FIFO) buffer. The link state change information indicates the first link state, the duration of time the C2C link was in the first link state, and the speed of the C2C link in the first link state. Upon detecting a request for link state change information, link state change information is retrieved from the FIFO buffer and transmitted serially to an output pin of the die, such as a general purpose input/output (GPIO) pin.

Abstract: A spinning device, comprising: (a) a base portion comprising: a base face; a side face; and a top face; a substantially ring-shaped groove extending upwardly from the base face, and a spinning edge portion between the side face and the base face; and (b) a top portion connected to the top face of the base portion, the device having a mass distribution balancing the device on the spinning edge portion while the device is spinning.

Abstract: Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. If address translation entries for a command are not found, the translation entries may be retrieved from memory. Address translations for subsequent commands depending from the command getting the miss may be preserved until the address translation entry is retrieved from memory. Therefore, retranslation of addresses for subsequent commands is avoided.

Abstract: Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue while handling multiple translation cache misses. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. During address translation, if a translation cache miss occurs while an outstanding miss is being handled, the pipeline may be stalled and the command causing the second miss and all subsequent commands may be processed again after the first miss is handled.

Abstract: A method and apparatus for the prevention of unwanted access to secure areas of memory during the POR or boot sequence of a CPU. Via control within the CPU, commands that are sent to and received by the CPU prior to the finish of the POR sequence can be denied I/O address translation, thus protecting memory during the POR sequence. Furthermore, an error response can be generated in the CPU and sent back to the I/O device which issued the command.

Abstract: Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue while handling translation cache misses. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. During address translation, if a translation cache miss occurs the relevant translation cache entries may be retrieved from memory. After the relevant entries are retrieved a notification may be sent requesting reissue of the command getting the translation cache miss.

Abstract: In a first aspect, a first method is provided for aligning data. The first method includes the steps of (1) transmitting identical reference data from first logic to second logic on each of a plurality of busses coupling the first logic to the second logic; (2) determining values indicative of time skews among the busses; and (3) configuring alignment logic based on the values such that the alignment logic aligns the reference data received from each of the plurality of busses. Numerous other aspects are provided.

Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) receiving a set of data; (2) determining whether a free group entry of a size required by a portion of the set of data exists in one of a plurality of sections of a memory; (3) if a free group entry of the size required by the portion of the set of data does not exist in one of the plurality of sections of the memory, determining whether the memory includes one or more sections of an unallocated size; and (4) if the memory includes one or more sections of an unallocated size, allocating one of the sections of an unallocated size to the size required by the portion of the set of data thereby creating a section of a dynamically allocated size. Numerous other aspects are provided.