Abstract: A processor for performing a predetermined computational operation in which one or multiple data element(s) is/are used to determine a result. The processor includes one or more processor core(s) and at least one buffer memory, connectable to a main memory, and if the main memory is connected, it is designed to access the main memory. Each processor core is designed to execute instructions. The at least one buffer memory includes a calculation circuit which is designed to perform the computational operation in response to an execution signal if the one or the multiple data element(s) is/are stored in the buffer memory, the result being stored in the buffer memory. The processor is designed to perform the computational operation optionally using one of the processor cores with the aid of the instructions or to perform it in the at least one buffer memory using the respective calculation circuit.

Abstract: An apparatus including a first comparator device. The first comparator device includes a first reference current providing device for providing a first reference current and a first comparison current providing device for providing a first comparison current. The first comparator device is configured to compare the first reference current with the first comparison current to obtain a first comparison result and output a first output signal characterizing the first comparison result based on the first comparison result.

Abstract: A memory device comprising a plurality of memory cells situated in a first cell field, multiple first bit lines, each respectively connected to multiple memory cells of the first cell field to enable access to the memory cells via the bit line, and multiple sense amplifier pairs which respectively comprise a first and a second sense amplifier. Each first bit line is assigned to a sense amplifier pair, each first bit line being connected to a respective first semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the first sense amplifier of the sense amplifier pair, to which the bit line is assigned. Each first bit line is connected to a respective second semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the second sense amplifier of the sense amplifier pair, to which the bit line is assigned.

Abstract: A memory device comprising a cell field having memory cells, N bit lines, which are respectively connected to at least one of the memory cells of the cell field, N being a whole number greater than one, N sense amplifiers; a bit shift circuit, which has S switch element rows, S being a whole number greater than one and a row number in the range from zero to S?1 being assignable to each switch element row. Each switch element row includes at least one semiconductor switch element connected to one of the bit lines and one of the sense amplifiers. Switch elements of each row connect all bit lines, whose bit line number is smaller than or equal to N minus the row number, to sense amplifiers, so that the respective sense amplifier number is equal to the respective bit line number plus the row number.

Abstract: A scalar product circuit for computing a binary scalar product of an input vector and a weight vector. The scalar product circuit includes one or multiple adders and at least one matrix circuit including memory cells that are arranged in multiple rows and multiple columns in the form of a matrix, each memory cell including a first memory state and a second memory state. Each matrix circuit includes at least one weight range including one or multiple bit sections, the matrix circuit including an analog-to-digital converter and a bit shifting unit connected thereto for each bit section, the column lines of the bit section being connected to the analog-to-digital converter, and a column selection switching element being provided for each column. The bit shifting units are connected to one of the adders, those bit shifting units that are included in a weight range being connected to the same adder.

Abstract: A device including a first comparator unit, the first comparator unit including a first reference current provision unit for providing a first reference current and a first comparison current provision unit for providing a first comparison current, and the first comparator unit being designed to compare the first reference current with the first comparison current in order to obtain a first comparison result and, based on the first comparison result, to influence at least one reference current and/or at least one comparison current of at least one further comparator unit.

Abstract: A method for executing one or multiple vector matrix operations using a matrix operation circuit. The method includes: receiving an input vector having a plurality of input values; applying and increasing row voltages on row lines of the matrix, wherein the row voltages are increased linearly starting from zero, and for each of the row voltages, a rate of increase is proportional to one of the input values; detecting the output currents generated at the current outputs; comparing current intensities of the detected output currents to a predetermined limit current intensity; terminating the increase of the row voltages, if, upon comparison, it is established that at least one of the output currents has a current intensity which is greater than the limit current intensity; and determining one or multiple output vectors having a plurality of output values on the basis of the measured currents.

Abstract: A processor for performing a predetermined computational operation in which one or multiple data element(s) is/are used to determine a result. The processor includes one or more processor core(s) and at least one buffer memory, connectable to a main memory, and if the main memory is connected, it is designed to access the main memory. Each processor core is designed to execute instructions. The at least one buffer memory includes a calculation circuit which is designed to perform the computational operation in response to an execution signal if the one or the multiple data element(s) is/are stored in the buffer memory, the result being stored in the buffer memory. The processor is designed to perform the computational operation optionally using one of the processor cores with the aid of the instructions or to perform it in the at least one buffer memory using the respective calculation circuit.

Abstract: An apparatus including a first comparator device. The first comparator device includes a first reference current providing device for providing a first reference current and a first comparison current providing device for providing a first comparison current. The first comparator device is configured to compare the first reference current with the first comparison current to obtain a first comparison result and output a first output signal characterizing the first comparison result based on the first comparison result.

Abstract: The present disclosure relates to a method comprising: receiving (201) acquired k-space data of an object, reconstructing (203) an image from the acquired k-space data, generating (205) reconstructed k-space data from the reconstructed image, determining (207) delta k-space data as a difference between the acquired k-space data and the reconstructed k-space data, splitting (209) the k-space data into one or more data chunks, wherein each data chunk of the data chunks comprises a set of one or more samples having a set of k-space coordinates, for each set of k-space coordinates of the one or more sets of coordinates, selecting (211), from the delta k-space data, a residual data set having the set of k-space coordinates, inputting (213) at least part of the data chunks and corresponding residual data sets to a trained machine learning model, thereby obtaining from the trained machine learning model probabilities of motion corruption for each of the data chunks of the acquired k-space.

Abstract: A TiO2-graphene-silver hybrid nanocomposite and a method of preparing the TiO2-graphene-silver hybrid nanocomposite is disclosed. The TiO2-graphene-silver hybrid nanocomposite at an average particle size ranging from 12-15 nanometers and having a surface area of 140.5 m2/g includes titanium oxide, graphene oxide and silver, the silver ranging from about 2 weight % to 10 weight %. The method of preparation includes introducing sol gel to a microwave irradiation to prepare an irradiated sample of TiO2-graphene oxide sample, wherein the sol gel includes TiO2 containing gel along with graphene containing sol, followed by adding AgNO3 solution to the TiO2-graphene oxide sample for preparing a TiO2-graphene-silver hybrid suspension. The TiO2-graphene-silver hybrid suspension undergoes microwave irradiation to prepare dried TiO2-graphene-silver hybrid composite.

Abstract: A TiO2-graphene-silver hybrid nanocomposite and a method of preparing the TiO2-graphene-silver hybrid nanocomposite is disclosed. The TiO2-graphene-silver hybrid nanocomposite at an average particle size ranging from 12-15 nanometers and having a surface area of 140.5 m2/g includes titanium oxide, graphene oxide and silver, the silver ranging from about 2 weight % to 10 weight %. The method of preparation includes introducing sol gel to a microwave irradiation to prepare an irradiated sample of TiO2-graphene oxide sample, wherein the sol gel includes TiO2 containing gel along with graphene containing sol, followed by adding AgNO3 solution to the TiO2-graphene oxide sample for preparing a TiO2-graphene-silver hybrid suspension. The TiO2-graphene-silver hybrid suspension undergoes microwave irradiation to prepare dried TiO2-graphene-silver hybrid composite.