Patents by Inventor Ibukun Oluwagbenga Olumuyiwa

Ibukun Oluwagbenga Olumuyiwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Real time counter-based method for the determination and measurement of frequency lock time in phase-locked loops
    Patent number: 11070218
    Abstract: A system to test a PLL circuit driven by a reference clock includes a first counter coupled to a reference clock output, a first buffer coupled to the first counter, a second counter coupled to a controlled-oscillator (CO) output of the PLL circuit, a second buffer coupled to the second counter, and a processor configured to compute a PLL lock time according to second count values in the second buffer, and to compute a PLL startup slope according to the first count values in the first buffer and the second count values in the second buffer. A method includes powering up a PLL circuit of a wafer, sampling count values of a reference clock and second count values of the PLL circuit and computing a PLL performance parameter according to the sampled count values in a buffer.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: July 20, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Ibukun Oluwagbenga Olumuyiwa, Nirav Narendrakumar Ginwala
  • REAL TIME COUNTER-BASED METHOD FOR THE DETERMINATION AND MEASUREMENT OF FREQUENCY LOCK TIME IN PHASE-LOCKED LOOPS
    Publication number: 20200336151
    Abstract: A system to test a PLL circuit driven by a reference clock includes a first counter coupled to a reference clock output, a first buffer coupled to the first counter, a second counter coupled to a controlled-oscillator (CO) output of the PLL circuit, a second buffer coupled to the second counter, and a processor configured to compute a PLL lock time according to second count values in the second buffer, and to compute a PLL startup slope according to the first count values in the first buffer and the second count values in the second buffer. A method includes powering up a PLL circuit of a wafer, sampling count values of a reference clock and second count values of the PLL circuit and computing a PLL performance parameter according to the sampled count values in a buffer.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 22, 2020
    Applicant: Texas Instruments Incorporated
    Inventors: Ibukun Oluwagbenga Olumuyiwa, Nirav Narendrakumar Ginwala