Patents by Inventor Ichihiko Toyoda

Ichihiko Toyoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6150897
    Abstract: A Marchand balun cirucit having a pair of coupled lines of quarter wavelength for dividing and/or combining signals with the same amplitude and opposite phase with each other is improved by inserting a cancellation element between said pair of coupled lines. Said cancellation element may be a transmission line, a capacitor, or an inductor which improves amplitude difference error and phase difference error of a pair of outputs by controlling phase velocity for an even mode so that phase velocity for an even mode becomes equal to that for an odd mode. Thus, a balun circuit with wide operation band, and less error of amplitude difference and phase difference is obtained.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: November 21, 2000
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Kenjiro Nishikawa, Ichihiko Toyoda, Tsuneo Tokumitsu
  • Patent number: 5973575
    Abstract: A voltage controlled oscillator for wide tuning range of frequency with less phase noise has a bipolar transistor provided with a positive feedback circuit between a base and an emitter of the transistor, an impedance matching circuit coupled with a collector of the transistor and an output terminal, a resistor coupled between the base of the transistor and a control source which provides control voltage for adjusting oscillation frequency of the oscillator. The base of the transistor shows capacitive negative impedance, and an inductive element is coupled with the base of the transistor for oscillation. The emitter of the transistor is grounded for D.C. voltage through an inductor or a transmission line, or coupled with a control voltage.
    Type: Grant
    Filed: February 12, 1998
    Date of Patent: October 26, 1999
    Assignee: Nippon Telegraph and Telephone Corp.
    Inventors: Kenji Kamogawa, Kenjiro Nishikawa, Ichihiko Toyoda, Tsuneo Tokumitsu
  • Patent number: 5739560
    Abstract: A monolithic integrated circuit utilizing areas associated with unused devices for wiring signal lines, thereby implementing effective wiring and improving high frequency characteristics. A common substrate consisting of a semiconductor substrate, and active devices, capacitor electrodes and resistors formed on the semiconductor substrate, is followed by a dielectric film, a ground metal, a dielectric film whose thickness is equal to or greater than 1 .mu.m, and signal lines. A desired circuit is formed by connecting the signal lines with electrodes of the active devices and other elements via, holes in the dielectric films, and windows of the ground metal. The windows of the ground metal are formed over portions of active devices which are used as components of the circuit.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: April 14, 1998
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Ichihiko Toyoda, Tsuneo Tokumitsu, Kenjiro Nishikawa, Kenji Kamogawa
  • Patent number: 5652157
    Abstract: A new design concept is presented and demonstrated for the fabrication of active and passive components in integrated circuit (IC) devices for microwave signal transmission. High circuit packing density is desirable but the current configurations of the conventional flat strip type conductors present physical limitations to achieving such an objective. The new conductor configuration not only overcomes such circuit packing problems of the conventional line design, but provides additional improvements in performance parameters, such as lower resistance and lower parasitic interactions, an ability to fabricate circuits to design specifications and to improve reliability at low cost. The new concept has been applied to the fabrication of transmission lines, capacitors, inductors, air bridges and to formulating the fabrication steps for a FET. Polyamide film enables an improved fabrication step to be performed in the invention, and a new processing technique for polyimide material has also been demonstrated.
    Type: Grant
    Filed: February 28, 1996
    Date of Patent: July 29, 1997
    Assignee: Nippon Telegraph And Telephone Corporation
    Inventors: Makoto Hirano, Kazuyoshi Asai, Yuhki Imai, Masami Tokumitsu, Tsuneo Tokumitsu, Ichihiko Toyoda
  • Patent number: 5639686
    Abstract: A new design concept is presented and demonstrated for the fabrication of active and passive components in integrated circuit (IC) devices for microwave signal transmission. High circuit packing density is desirable but the current configurations of the conventional flat strip type conductors present physical limitations to achieving such an objective. The new conductor configuration not only overcomes such circuit packing problems of the conventional line design, but provides additional improvements in performance parameters, such as lower circuit resistance and lower parasitic interactions; an ability to fabricate circuits to design specifications and to improve reliability at low cost. The new concept has been applied to the fabrication of transmission lines, capacitors, inductors, air bridges and to formulating the fabrication steps for a FET.
    Type: Grant
    Filed: October 7, 1993
    Date of Patent: June 17, 1997
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Hirano, Kazuyoshi Asai, Yuhki Imai, Masami Tokumitsu, Tsuneo Tokumitsu, Ichihiko Toyoda
  • Patent number: 5634208
    Abstract: A hybrid including a substrate, a first dielectric layer, a ground metal, and a second dielectric layer, which are stacked in this order. Transmission lines are formed below and above the ground metal, and a slit is formed in the ground metal at a position corresponding to projection of the transmission lines onto the ground metal. The substrate has a greater dielectric constant than the dielectric layers. This makes it possible to prevent coupling between the upper and lower transmission lines, thereby implementing a high impedance, low loss transmission lines.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: May 27, 1997
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Kenjiro Nishikawa, Ichihiko Toyoda, Tsuneo Tokumitsu, Kenji Kamogawa
  • Patent number: 5550068
    Abstract: A new design concept is presented and demonstrated for the fabrication of active and passive components in integrated circuit (IC) devices for microwave signal transmission. High circuit packing density is desirable but the current configurations of the conventional flat strip type conductors present physical limitations to achieving such an objective. The new conductor configuration not only overcomes such circuit packing problems of the conventional line design, but provides additional improvements in performance parameters, such as lower circuit resistance and lower parasitic interactions; an ability to fabricate circuits to design specifications and to improve reliability at low cost. The new concept has been applied to the fabrication of transmission lines, capacitors, inductors, air bridges and to formulating the fabrication steps for a FET.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: August 27, 1996
    Assignee: Nippon Telegraph And Telephone Corporation
    Inventors: Makoto Hirano, Kazuyoshi Asai, Yuhki Imai, Masami Tokumitsu, Tsuneo Tokumitsu, Ichihiko Toyoda
  • Patent number: 5281769
    Abstract: A new design concept is presented and demonstrated for the fabrication of active and passive components in integrated circuit (IC) devices for microwave signal transmission. High circuit packing density is desirable but the current configurations of the conventional flat strip type conductors present physical limitations to achieving such an objective. The new conductor configuration not only overcomes such circuit packing problems of the conventional line design, but provides additional improvements in performance parameters, such as lower circuit resistance and lower parasitic interactions; an ability to fabricate circuits to design specifications and to improve reliability at low cost. The new concept has been applied to the fabrication of transmission lines, capacitors, inductors, air bridges and to formulating the fabrication steps for a FET.
    Type: Grant
    Filed: November 4, 1991
    Date of Patent: January 25, 1994
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Hirano, Kazuyoshi Asai, Yuhki Imai, Masami Tokumitsu, Tsuneo Tokumitsu, Ichihiko Toyoda