Patents by Inventor Ichiro Abe

Ichiro Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10833087
    Abstract: A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fredrick D. Fishburn, Haitao Liu, Soichi Sugiura, Oscar O. Enomoto, Mark A. Zaleski, Keisuke Hirofuji, Makoto Morino, Ichiro Abe, Yoshiyuki Nanjo, Atsuko Otsuka
  • Publication number: 20200066726
    Abstract: A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: Fredrick D. Fishburn, Haitao Liu, Soichi Sugiura, Oscar O. Enomoto, Mark A. Zaleski, Keisuke Hirofuji, Makoto Morino, Ichiro Abe, Yoshiyuki Nanjo, Atsuko Otsuka
  • Patent number: 8576647
    Abstract: A semiconductor device includes a bit line; a data bus line corresponding to the bit line; a selection transistor that controls electrical connection between the bit line and the data bus line; a write amplifier that writes data to the bit line through the data bus; and a test circuit. The test circuit sets the bit line to a first potential during a test period regardless of an operation of the write amplifier, sets the data bus line to a second potential and then sets the data bus line in a floating state to detect transition of the data bus line from the second potential to the first potential, with the selection transistor being activated to electrically connect the bit line and the data bus line.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: November 5, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Yuya Yamada, Ichiro Abe
  • Publication number: 20120113734
    Abstract: A semiconductor device includes a bit line; a data bus line corresponding to the bit line; a selection transistor that controls electrical connection between the bit line and the data bus line; a write amplifier that writes data to the bit line through the data bus; and a test circuit. The test circuit sets the bit line to a first potential during a test period regardless of an operation of the write amplifier, sets the data bus line to a second potential and then sets the data bus line in a floating state to detect transition of the data bus line from the second potential to the first potential, with the selection transistor being activated to electrically connect the bit line and the data bus line.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 10, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yuya YAMADA, Ichiro ABE
  • Patent number: 7881141
    Abstract: In order to successively perform refresh operations, a semiconductor device has a plurality of regions performing a repair independently from each other, even when the repair is carried out in the region by a replacement with a repair memory block included in a plate included in each region. Specifically, the successive refresh operations are performed by alternately activating word lines in the respective regions so as to ensure a sufficiently long precharge period.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: February 1, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Ichiro Abe
  • Patent number: 7573309
    Abstract: Disclosed is waveform width adjusting circuit that comprises: a delay circuit having a prescribed delay time is provided in a signal propagation path and a delay adjusting circuit which applies an adjustment in such a manner that when a waveform width extending from either a positive-going transition or a negative-going transition of the signal waveform at an input terminal to the next negative-going transition or positive-going transition is greater than the delay time of the delay circuit, a signal having a reduced waveform width is output, and such that when the waveform width of the signal at the input terminal is less than or equal to the delay time, the waveform width is not reduced and the signal that is output has the waveform width of the original signal. Thus, the waveform width of a signal for which the waveform width is less than a limit is not reduced.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: August 11, 2009
    Assignee: Elpida Memory, Inc.
    Inventor: Ichiro Abe
  • Publication number: 20090109773
    Abstract: In order to successively perform refresh operations, a semiconductor device has a plurality of regions performing a repair independently from each other, even when the repair is carried out in the region by a replacement with a repair memory block included in a plate included in each region. Specifically, the successive refresh operations are performed by alternately activating word lines in the respective regions so as to ensure a sufficiently long precharge period.
    Type: Application
    Filed: October 29, 2008
    Publication date: April 30, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Ichiro ABE
  • Publication number: 20070252628
    Abstract: Disclosed is waveform width adjusting circuit that comprises: a delay circuit having a prescribed delay time is provided in a signal propagation path and a delay adjusting circuit which applies an adjustment in such a manner that when a waveform width extending from either a positive-going transition or a negative-going transition of the signal waveform at an input terminal to the next negative-going transition or positive-going transition is greater than the delay time of the delay circuit, a signal having a reduced waveform width is output, and such that when the waveform width of the signal at the input terminal is less than or equal to the delay time, the waveform width is not reduced and the signal that is output has the waveform width of the original signal. Thus, the waveform width of a signal for which the waveform width is less than a limit is not reduced.
    Type: Application
    Filed: April 26, 2007
    Publication date: November 1, 2007
    Applicant: Elpida Memory, Inc.
    Inventor: Ichiro Abe
  • Patent number: 7262642
    Abstract: Disclosed is a semiconductor integrated circuit that comprises first and second transmission systems, each comprising a plurality of transistors; and an output select unit. Transistors constituting said first transmission system comprise transistors having relatively high threshold values and being turned off and transistors having relatively low threshold values and being turned on, when the input signal supplied to said first transmission system takes a first value; and transistors constituting said second transmission system, comprise transistors having relatively high threshold values and being turned off and transistors have relatively low threshold values and being turned on, when an input signal supplied to said second transmission system assumes a second value.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: August 28, 2007
    Assignee: Elpida Memory, Inc.
    Inventor: Ichiro Abe
  • Publication number: 20060038593
    Abstract: Disclosed is a semiconductor integrated circuit that comprises first and second transmission systems receiving in common an input signal supplied to a signal input terminal and having substantially identical logic configuration to each other, each comprising a plurality of transistors; and an output select unit. Transistors constituting said first transmission system comprise transistors having relatively high threshold values and being turned off and transistors having relatively low threshold values and being turned on, when the input signal supplied to said first transmission system takes a first value; and transistors constituting said second transmission system, comprise transistors having relatively high threshold values and being turned off and transistors have relatively low threshold values and being turned on, when an input signal supplied to said second transmission system assumes a second value.
    Type: Application
    Filed: August 16, 2005
    Publication date: February 23, 2006
    Inventor: Ichiro Abe
  • Patent number: 6143149
    Abstract: A sputtering apparatus is provided with a wafer holder disposed in a chamber. A wafer is placed on the wafer holder. A target is disposed in the chamber such as to be opposed to the wafer on the wafer holder. The target is divided into a plurality of pieces. In the sputtering apparatus, there are provided a gas controlling device which exhausts air from the chamber and introduces sputtering gas into the chamber, and a power source device which applies voltage to the target. The power source device individually controls the voltage to be applied to each of the divided targets. A shield member is provided in the chamber. The shield member partitions the chamber in correspondence to the divided targets.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: November 7, 2000
    Assignee: NEC Corporation
    Inventor: Ken-ichiro Abe
  • Patent number: 4944832
    Abstract: A label peeler for peeling off a label attached to a side of a container such as a bottle includes a holder for holding the container, label scraping means for scraping the label off the container by effecting sliding movement in intimate contact with the side of the container, and driving means for varying the relative position of the container and the lavel scraping means to remove the label from the side of the container. With the container being held by the holder, the holder or the label scraping means or both are moved to vary the relative position of the container and the label scraping means while keeping the label scraping means in close contact with the side of the container, for thereby mechanically peeling the label off the container.
    Type: Grant
    Filed: January 25, 1989
    Date of Patent: July 31, 1990
    Assignee: Kirin Beer Kabushiki Kaisha
    Inventors: Ichiro Abe, Toshio Suzuki
  • Patent number: 4918902
    Abstract: The lower edge of the peripheral wall of a can cap and the upper edge of a can barrel are spaced from each other by a gap therebetween. Streams of an inert gas from different groups of injector nozzles are injected, from outside of the gap, through the gap into the can cap and the can barrel, respectively, to replace air in the can cap and the can barrel with the injected gas. Then, the can barrel is fitted in to the can cap, and welded thereto to entrap the injected gas in the can barrel and the can cap.
    Type: Grant
    Filed: July 29, 1988
    Date of Patent: April 24, 1990
    Assignees: Hokkai Can Co., Ltd., Kirin Brewery Co., Ltd.
    Inventors: Tohru Honma, Shigeki Mori, Kunihiko Ohya, Shiro Matsumoto, Akira Nakata, Ichiro Abe, Naoto Hosaka
  • Patent number: 4911602
    Abstract: A container supply system supplies a plurality of containers such bottles encased in a box to a container processing machine such as a bottle washing machine. The container supply system includes a box reverser for reversing the box with the bottles encased therein, a container holder disposed for holding the bottles discharged from the reversed box and thereafter releasing the bottles, a container receiver having a plurality of container receiver members for receiving the bottles, respectively, and a container ejector having a plurality of container ejector members for pushing the bottles from the container receiver to the container processing machine. In one embodiment, the container receiver is positioned below the box reverser. In another embodiment, the box reverser and the container receiver are spaced from each other, and a delivery carriage is provided for receiving the containers from the box reverser and delivering the received containers to the container receiver.
    Type: Grant
    Filed: June 16, 1989
    Date of Patent: March 27, 1990
    Assignee: Kirin Beer Kabushiki Kaisha
    Inventor: Ichiro Abe
  • Patent number: 4308818
    Abstract: Apparatus for coating with a desired substance a succession of beverage bottles traveling along an arcuate guideway. A star wheel assembly, rotatable about an axis at which the arcuate guideway is centered, feeds the successive bottles along the guideway, further coacting with the opposed guideway-defining surface to cause rotation of each bottle about its own axis. Coaxially mounted on the star wheel assembly, either for simultaneous rotation therewith or for independent rotation, one or more annular rows of discrete coating bodies or one or more coating rolls apply the coating substance to the successive bottles, creating one or more band-shaped coatings around each bottle. In one embodiment the star wheel assembly is replaced by a feed roll assembly comprising a pair of annular rows of independently rotatable feed rolls.
    Type: Grant
    Filed: April 3, 1980
    Date of Patent: January 5, 1982
    Assignee: Kirin Beer Kabushiki Kaisha
    Inventors: Ichiro Abe, Takashi Suzuki, Toshio Ebara
  • Patent number: 4274533
    Abstract: In a system for conveying bottles or like articles, bottles being conveyed in single file along two or more separate paths are caused to merge and travel in single file along a single path by a device comprising arcuate guide passages and star wheels rotatably supported in concentric relation thereto, each star wheel having a plurality of teeth with respective outer tips lying in a rotational path extending partly into the guide passage, each tooth having a special profile shape defined by leading and trailing edges, the leading edge having a concave arcuate shape of a radius of curvature which substantially corresponds to the radius of said circular cross section and extending from the tip inward to smoothly join the inner end of the trailing edge of the forwardly adjacent tooth, said trailing edge having a convex curved shape and extending outward to the tip of said adjacent tooth, said leading and trailing edges thereby forming a fair S-shaped curve.
    Type: Grant
    Filed: June 5, 1979
    Date of Patent: June 23, 1981
    Assignee: Kirin Beer Kabushiki Kaisha
    Inventor: Ichiro Abe