Patents by Inventor Ichiro Doi

Ichiro Doi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130269992
    Abstract: An insulating structure is formed that favorably maintains gap-fill capability of a narrow width pattern in a memory cell while also preventing the formation of cracks in an insulator in a peripheral circuit, and has the memory cell and peripheral circuit within the same layer. The present invention provides an insulating structure comprising a substrate and a circuit pattern formed on the substrate, wherein the circuit pattern has a narrow width region having a narrow width pattern of a width of 30 nm or less and a wide width region having a wide width pattern of a width of greater than 100 nm in the same layer, and the same insulating composition is formed within the narrow width pattern and within the wide width pattern.
    Type: Application
    Filed: December 22, 2011
    Publication date: October 17, 2013
    Applicant: ASAHI KASEI E-MATERIALS CORPORATION
    Inventors: Ichiro Doi, Shozo Takada, Reiko Mishima, Hideo Saito
  • Patent number: 6479374
    Abstract: Disclosed is a method for producing a circuit structure having an insulator layer comprising a porous silicon oxide thin film, which comprises (1) forming a preliminary insulator layer comprising a silicon oxide-organic polymer composite thin film formed on a substrate, which silicon oxide-organic polymer composite thin film comprises a silicon oxide having an organic polymer dispersed therein, (2) forming, in the preliminary insulator layer, a groove which defines a pattern for a circuit, (3) forming, in the groove, a metal layer which functions as a circuit, and (4) removing the organic polymer from the preliminary insulator layer to render the preliminary insulator layer porous, thereby converting the preliminary insulator layer to an insulator layer comprising a porous silicon oxide thin film. By the method of the present invention, the capacitance between mutually adjacent circuit lines (line-to-line capacitance) in the circuit structure can be lowered.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: November 12, 2002
    Assignee: Asahi Kasei Kabushiki Kaisha
    Inventors: Takaaki Ioka, Tsuneaki Tanabe, Ichiro Doi
  • Patent number: 6041096
    Abstract: A method and an apparatus for total reflection X-ray fluorescence spectroscopy which facilitates total reflection X-ray fluorescent spectroscopy of a sample having irregularities.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: March 21, 2000
    Assignee: Asahi Kasei Kogyo Kabushiki Kaisha
    Inventors: Ichiro Doi, Shoichiro Tonomura
  • Patent number: 4748078
    Abstract: A warp knitted lace fabric comprising a plurality of chain stitches and a ground insertion yarn, pattern yarn and/or other yarn interconnecting said chain stitches, said plurality of chain stitches being made either as a whole or in part by a heat bonding yarn comprising a lace knitting yarn carrying a low-melting thermoplastic synthetic resin covering and said heat bonding yarn being thermally jointed to itself or to other component yarns at intersections.
    Type: Grant
    Filed: December 5, 1986
    Date of Patent: May 31, 1988
    Assignee: Sakae Lace Co., Ltd.
    Inventors: Ichiro Doi, Katsuhiko Ichii