Patents by Inventor Ichiro Fujiwara

Ichiro Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230012093
    Abstract: The invention provides a non-volatile storage element and non-volatile storage device employing a ferroelectric material with low power consumption, excellent high reliability, and especially write/erase endurance, which can be mixed with advanced CMOS logic. The non-volatile storage element has at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between both conductive layers, with a buffer layer having oxygen ion conductivity situated between the ferroelectric layer and the first conductive layer and/or second conductive layer.
    Type: Application
    Filed: December 4, 2020
    Publication date: January 12, 2023
    Applicant: Tokyo Institute of Technology
    Inventors: Kuniyuki KAKUSHIMA, Hiroshi FUNAKUBO, Shun-ichiro OHMI, Joel MOLINA REYES, Ichiro FUJIWARA, Atsushi HORI, Takao SHIMIZU, Yoshiko NAKAMURA, Takanori MIMURA
  • Patent number: 10682330
    Abstract: In order to reduce the side effects of paclitaxel derivatives having excellent anti-cancer effects, an attempt was made to produce a liposome encapsulating paclitaxel derivatives such as paclitaxel monoglycosides and docetaxel monoglycosides. However, the introduction efficiency of paclitaxel derivatives, etc., into a liposome was poor, and this technique was not developed to a practical level. The present invention provides a method for producing a liposome encapsulating a paclitaxel monoglycoside and/or a docetaxel monoglycoside, and having an antibody specifically recognizing a cancer cell, the method comprising a step of bringing a liposome encapsulating a polyoxyethylene ester derivative, a lower alcohol, and a buffer or water into contact with a solution in which a paclitaxel monoglycoside and/or a docetaxel monoglycoside is dissolved in an alkylene glycol-containing buffer or water.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: June 16, 2020
    Assignees: ENSUIKO SUGAR REFINING CO., LTD., HIROKI HAMADA, YOSHIO SHIMIZU, NATIONAL UNIVERSITY CORPORATION OKAYAMA UNIVERSITY
    Inventors: Hiroki Hamada, Ichiro Fujiwara, Masaharu Seno, Tomonari Kasai, Tsukasa Shigehiro, Masaharu Murakami, Katsuhiko Mikuni
  • Publication number: 20180280300
    Abstract: An object of the present invention is to provide a method for encapsulating a poorly water-soluble pharmacologically active substance in a liposome with high efficiency. The present invention provides a composition comprising a lipid having a phosphatidylcholine group, a cholesterol compound, a lipid having a phosphatidylethanolamine group, and a poorly water-soluble pharmacologically active substance, wherein the molar ratio of the lipid having a phosphatidylcholine group, the cholesterol compound, the lipid having a phosphatidylethanolamine group, and the poorly water-soluble pharmacologically active substance is 3 to 8:2 to 7:0.1 to 3:0.001 to 5, respectively.
    Type: Application
    Filed: October 6, 2016
    Publication date: October 4, 2018
    Applicants: ENSUIKO SUGAR REFINING CO., LTD., National University Corporation Okayama University
    Inventors: Hiroki HAMADA, Masaharu SENO, Tomonari KASAI, Tsukasa SHIGEHIRO, Koji HARA, Tetsuya ITO, Ichiro FUJIWARA
  • Patent number: 10074690
    Abstract: A semiconductor device including: a first member including a selection transistor on a front surface side of a first substrate; and a second member including a resistance change device and a connection layer that comes in contact with the resistance change device, the connection layer being bonded to a back surface of the first member.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 11, 2018
    Assignee: SONY CORPORATION
    Inventors: Mitsuharu Shoji, Ichiro Fujiwara
  • Publication number: 20170033157
    Abstract: A semiconductor device including: a first member including a selection transistor on a front surface side of a first substrate; and a second member including a resistance change device and a connection layer that comes in contact with the resistance change device, the connection layer being bonded to a back surface of the first member.
    Type: Application
    Filed: October 11, 2016
    Publication date: February 2, 2017
    Inventors: Mitsuharu Shoji, Ichiro Fujiwara
  • Patent number: 9502467
    Abstract: A semiconductor device includes: a first member including a selection transistor on a front surface side of a first substrate; and a second member including a resistance change device and a connection layer that comes in contact with the resistance change device, the connection layer being bonded to a back surface of the first member.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: November 22, 2016
    Assignee: SONY CORPORATION
    Inventors: Mitsuharu Shoji, Ichiro Fujiwara
  • Publication number: 20160256566
    Abstract: In order to reduce the side effects of paclitaxel derivatives having excellent anti-cancer effects, an attempt was made to produce a liposome encapsulating paclitaxel derivatives such as paclitaxel monoglycosides and docetaxel monoglycosides. However, the introduction efficiency of paclitaxel derivatives, etc., into a liposome was poor, and this technique was not developed to a practical level. The present invention provides a method for producing a liposome encapsulating a paclitaxel monoglycoside and/or a docetaxel monoglycoside, and having an antibody specifically recognizing a cancer cell, the method comprising a step of bringing a liposome encapsulating a polyoxyethylene ester derivative, a lower alcohol, and a buffer or water into contact with a solution in which a paclitaxel monoglycoside and/or a docetaxel monoglycoside is dissolved in an alkylene glycol-containing buffer or water.
    Type: Application
    Filed: March 22, 2013
    Publication date: September 8, 2016
    Applicants: ENSUIKO SUGAR REFINING CO., LTD., NATIONAL UNIVERSITY CORPORATION OKAYAMA UNIVERSITY
    Inventors: Hiroki HAMADA, Ichiro FUJIWARA, Masaharu SENO, Tomonari KASAI, Tsukasa SHIGEHIRO, Masaharu MURAKAMI, Katsuhiko MIKUNI
  • Publication number: 20150056270
    Abstract: In order to reduce the side effects of paclitaxel derivatives having excellent anti-cancer effects, an attempt was made to produce a liposome encapsulating paclitaxel derivatives such as paclitaxel monoglycosides and docetaxel monoglycosides. However, the introduction efficiency of paclitaxel derivatives, etc., into a liposome was poor, and this technique was not developed to a practical level. The present invention provides a method for producing a liposome encapsulating a paclitaxel monoglycoside and/or a docetaxel monoglycoside, and having an antibody specifically recognizing a cancer cell, the method comprising a step of bringing a liposome encapsulating a polyoxyethylene ester derivative, a lower alcohol, and a buffer or water into contact with a solution in which a paclitaxel monoglycoside and/or a docetaxel monoglycoside is dissolved in an alkylene glycol-containing buffer or water.
    Type: Application
    Filed: March 22, 2013
    Publication date: February 26, 2015
    Inventors: Hiroki Hamada, Ichiro Fujiwara, Masaharu Seno, Tomonari Kasai, Tsukasa Shigehiro, Masaharu Murakami, Katsuhiko Mikuni
  • Publication number: 20140346624
    Abstract: A semiconductor device includes: a first member including a selection transistor on a front surface side of a first substrate; and a second member including a resistance change device and a connection layer that comes in contact with the resistance change device, the connection layer being bonded to a back surface of the first member.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 27, 2014
    Applicant: Sony Corporation
    Inventors: Mitsuharu Shoji, Ichiro Fujiwara
  • Patent number: 8685786
    Abstract: Disclosed herein is a semiconductor memory device, including: a first electrode formed on a substrate; an ion source layer formed on an upper layer of the first electrode; and a second electrode formed on an upper layer of the ion source layer. Resistance change type memory cells in each of which either a surface of the first electrode or a surface of the ion source layer is oxidized to form a resistance change type memory layer in an interface between the first electrode and the ion source interface are arranged in a array.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 1, 2014
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Tetsuya Mizuguchi, Ichiro Fujiwara, Akira Kouchiyama, Satoshi Sasaki, Naomi Yamada
  • Publication number: 20130256626
    Abstract: Disclosed herein is a semiconductor memory device, including: a first electrode formed on a substrate; an ion source layer formed on an upper layer of the first electrode; and a second electrode formed on an upper layer of the ion source layer. Resistance change type memory cells in each of which either a surface of the first electrode or a surface of the ion source layer is oxidized to form a resistance change type memory layer in an interface between the first electrode and the ion source interface are arranged in a array.
    Type: Application
    Filed: May 24, 2013
    Publication date: October 3, 2013
    Inventors: Yoshihisa KAGAWA, Tetsuya MIZUGUCHI, Ichiro FUJIWARA, Akira KOUCHIYAMA, Satoshi SASAKI, Naomi YAMADA
  • Patent number: 7919806
    Abstract: Disclosed herein is a nonvolatile semiconductor memory device, including a memory transistor. The memory transistor has a channel formation region defined between two source and drain regions formed on a semiconductor substrate a bottom insulating film, a charge storage film and a top insulating film formed in order at least on the channel formation region, the charge storage film having a charge storage function, and a gate electrode formed on the top insulating film. The bottom insulating film is formed from a plurality of films containing nitrogen such that the content of nitrogen of a lowermost one of the films which contacts with the channel formation region and an uppermost one of the films which contacts with the gate electrode is higher than that of the other one or ones of the films which exist between the uppermost and lowermost films.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: April 5, 2011
    Assignee: Sony Corporation
    Inventors: Ichiro Fujiwara, Hiroshi Aozasa
  • Publication number: 20110031466
    Abstract: Disclosed herein is a semiconductor memory device, including: a first electrode formed on a substrate; an ion source layer formed on an upper layer of the first electrode; and a second electrode formed on an upper layer of the ion source layer. Resistance change type memory cells in each of which either a surface of the first electrode or a surface of the ion source layer is oxidized to form a resistance change type memory layer in an interface between the first electrode and the ion source interface are arranged in a array.
    Type: Application
    Filed: June 21, 2010
    Publication date: February 10, 2011
    Applicant: SONY CORPORATION
    Inventors: Yoshihisa KAGAWA, Tetsuya MIZUGUCHI, Ichiro FUJIWARA, Akira KOUCHIYAMA, Satoshi SASAKI, Naomi YAMADA
  • Patent number: 7521751
    Abstract: To provide a nonvolatile memory device suppressing a reduction of a data retention characteristic even if charges injected and stored into a local area of a nitride film is redistributed to achieve a reduction of voltage, the nonvolatile memory device in which hot electrons are injected into the local area of the nitride film at one or both of source•drain regions side to store data in a memory transistor is satisfied with a standard for evaluating a film quality of the nitride film, the standard being defined by one of the followings: a density of the bond group of silicon and hydrogen being under 1×1021 cm?3; an extinction coefficient in an ultraviolet region at a wavelength of 240 nm being under 0.10 or the extinction coefficient in 230 nm being under 0.14; an optical energy, a peak wavelength of an luminance spectrum, or a peak energy thereof.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: April 21, 2009
    Assignee: Sony Corporation
    Inventor: Ichiro Fujiwara
  • Publication number: 20080048241
    Abstract: Disclosed herein is a nonvolatile semiconductor memory device, including a memory transistor. The memory transistor has: a channel formation region defined between two source and drain regions formed on a semiconductor substrate; a bottom insulating film, a charge storage film and a top insulating film formed in order at least on the channel formation region, the charge storage film having a charge storage function, and a gate electrode formed on the top insulating film. The bottom insulating film is formed from a plurality of films containing nitrogen such that the content of nitrogen of a lowermost one of the films which contacts with the channel formation region and an uppermost one of the films which contacts with the gate electrode is higher than that of the other one or ones of the films which exist between the uppermost and lowermost films.
    Type: Application
    Filed: August 13, 2007
    Publication date: February 28, 2008
    Applicant: Sony Corporation
    Inventors: Ichiro Fujiwara, Hiroshi Aozasa
  • Patent number: 7259433
    Abstract: The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS1 made of silicon nitride or silicon oxynitride and a second nitride film CS2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS1. The first nitride film CS1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: August 21, 2007
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Hiroshi Aozasa, Ichiro Fujiwara, Shinji Tanaka
  • Patent number: 7227255
    Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: June 5, 2007
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
  • Patent number: 7145808
    Abstract: A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2a to 9) generate a first voltage (Vd) and a second voltage (Vg-Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg-Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: December 5, 2006
    Assignee: Sony Corporation
    Inventors: Ichiro Fujiwara, Hiromi Nobukata
  • Patent number: 7142451
    Abstract: A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2a to 9) generate a first voltage (Vd) and a second voltage (Vg?Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg?Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: November 28, 2006
    Assignee: Sony Corporation
    Inventors: Ichiro Fujiwara, Hiromi Nobukata
  • Patent number: 7102931
    Abstract: A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2a to 9) generate a first voltage (Vd) and a second voltage (Vg?Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg?Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: September 5, 2006
    Assignee: Sony Corporation
    Inventors: Ichiro Fujiwara, Hiromi Nobukata