Abstract: A semiconductor device includes an emitter layer: a base layer; and a collector layer, wherein the collector layer and the emitter layer each include a heavily doped thin sublayer having a high impurity concentration, and each of the heavily doped thin sublayers has an impurity concentration higher than those of semiconductor layers adjacent to each heavily doped thin sublayer.

Abstract: A semiconductor device includes an emitter layer: a base layer; and a collector layer, wherein the collector layer and the emitter layer each include a heavily doped thin sublayer having a high impurity concentration, and each of the heavily doped thin sublayers has an impurity concentration higher than those of semiconductor layers adjacent to each heavily doped thin sublayer.

Abstract: There is provided a semiconductor device capable of ensuring a complete enhancement-mode operation and realizing a power transistor excellent in the low-distortion, high-efficiency performance. On a surface of a substrate (1) composed of single crystal GaAs, a second barrier layer (3) composed of AlGaAs, a channel layer (4) composed of InGaAs, a third barrier layer (12) composed of InGaP and a first barrier layer (11) composed of AlGaAs are stacked in this order, while placing in between a buffer layer (2). Relation of ?1??3?0.5*(Eg3-Eg1), where ?1 is electron affinity of the first barrier layer (11), Eg1 is a band gap of the same, ?3 is electron affinity of the third barrier layer (12), and Eg3 is a band gap of the same, is satisfied between the first barrier layer (11) and the third barrier layer (12).

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III–V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n?-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III–V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n?-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III-V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n?-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III-V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n?-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III-V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n—GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: A semiconductor device having a heterojunction bipolar transistor capable of suppressing the deterioration of basic transistor characteristics, such as a decline of an injection efficiency from an emitter layer to a base layer due to the rising of emitter resistance, a decline of breakdown strength between the base layer and a collector layer, or a decline of reliability due to an introduction of a defect; configured to comprise a heterojunction bipolar transistor having an emitter layer, base layer and a collector layer, wherein an electron affinity of the base layer is smaller than that of the emitter layer and that of the collector layer, an interlayer is formed at least either between the emitter layer and the base layer or between the base layer and the collector layer, and the electron affinity of the interlayer has a value between the electron affinities of the two layers sandwiching the interlayer.

Abstract: A semiconductor device having a heterojunction bipolar transistor capable of suppressing deterioration of basic transistor characteristics, such as a decline of an injection efficiency from an emitter layer to a base layer due to rising of emitter resistance, a decline of breakdown strength between the base layer and a collector layer, or a decline of reliability due to an introduction of a defect; configured to comprise a heterojunction bipolar transistor having an emitter layer, base layer and a collector layer, wherein an electron affinity of the base layer is smaller than that of the emitter layer and that of the collector layer, an interlayer is formed at least either between the emitter layer and the base layer or between the base layer and the collector layer, and the electron affinity of the interlayer has a value between electron affinities of two layer sandwiching the interlayer.

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III-V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n−-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: A service center judges parts required for repair according to the trouble information received from a multi-functional peripheral (MFP), searches servicemen carrying repair parts based on the contents of the serviceman carrying parts memory, and contacts a portable terminal carried by an applicable servicemen. Then, by grasping the condition of the serviceman, e.g., whether he is in working, traveling or taking a rest, stores the condition of servicemen in the serviceman condition memory. In succession, based on the contents of the serviceman positioning memory, the serviceman condition memory and the MFP installation place memory, the service center searches a serviceman who is able to go most fast to the installing place of a MFP to be repaired among servicemen who carry required repair parts, and gives a repair direction to a portable terminal carried by this searched serviceman together the installing place of the MFP and contents of the trouble.

Abstract: A semiconductor device that is easily operated with a single positive voltage supply and exhibits an excellent linearity of mutual conductance and source-gate capacitance with regard to a gate voltage is provided. The semiconductor device comprises a second barrier layer of AlGaAs, a channel layer of InGaAs and a first barrier layer of AlGaAs that are stacked in this order on a substrate of GaAs with a buffer layer of u-GaAs between the substrate and the second barrier layer. Carrier supply regions doped with n-type impurity are formed in part of the first and second barrier layers. A low resistivity region including a high concentration of p-type impurity (Zn) is formed in the first barrier layer. The low resistivity region is buried in a high resistivity region and brought to contact with a gate electrode. Upon an application of positive voltage to the gate electrode, a carrier deficient region disappears in the channel layer and no parasitic resistance component remains.

Abstract: A semiconductor device, comprising: a channel layer formed on a substrate, the channel layer comprising a semiconductor; a first barrier layer formed on the channel layer, the first barrier layer comprising a semiconductor which has an electron affinity smaller than that of the semiconductor constituting the channel layer; a first gate contact layer formed on the first barrier layer, the first gate contact layer having a first conductive low-resistance region which comprises a semiconductor containing a first conductive impurity in a high concentration, wherein the sum of an electron affinity and a band-gap of the first gate contact layer is larger than an electron affinity of the channel layer by 1.3 eV or more; a gate electrode formed on the first gate contact layer; and a source electrode and a drain electrode formed on the first barrier layer with the gate electrode between, wherein the channel layer serves as a current passage between the source electrode and the drain electrode.

Abstract: A semiconductor device that is easily operated with a single positive voltage supply and exhibits an excellent linearity of mutual conductance and source-gate capacitance with regard to a gate voltage is provided. The semiconductor device comprises a second barrier layer of AlGaAs, a channel layer of InGaAs and a first barrier layer of AlGaAs that are stacked in this order on a substrate of GaAs with a buffer layer of u-GaAs between the substrate and the second barrier layer. Carrier supply regions doped with n-type impurity are formed in part of the first and second barrier layers. A low resistivity region including a high concentration of p-type impurity (Zn) is formed in the first barrier layer. The low resistivity region is buried in a high resistivity region and brought to contact with a gate electrode. Upon an application of positive voltage to the gate electrode, a carrier deficient region disappears in the channel layer and no parasitic resistance component remains.

Abstract: An electronic device comprises a conductive region, and a three-dimensional assembly of fine particles in a close relation with the conductive region, the conductive region being controlled in electric conductivity by controlling distribution of electrons in the three-dimensional assembly of fine particles. Another electronic device comprises a conductive region, and a two-dimensional assembly of fine particles in a close relation with the conductive region, the conductive region being controlled in electric conductivity by controlling the state of occupation by electrons in a plurality of quantum levels formed in the fine particles.

Abstract: A method of manufacturing a quantum device such as a coupled quantum boxes device are disclosed. The quantum device comprises: a semiconductor substrate; a plurality of box portions made of a first semiconductor; and a layer made of a second semiconductor provided on circumferences of the box portions, a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor. The manufacturing method comprises the steps of: making a plurality of box portions of a first semiconductor on a semiconductor substrate; and covering circumferences of the box portions with a layer of a second semiconductor, a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor.

Abstract: A method for vapor deposition includes monitoring of growth of a semiconductor layer by way of in-situ monitoring. According to the invention, in-situ monitoring is performed by irradiating a light beam onto the surface of the growing layer in a direction nearly perpendicular to the surface. Growth parameters of the layer are detected by monitoring variation of the light reflected by the surface of the layer. A growth condition in a vapor deposition chamber is feedback controlled based on the detected growth parameter.

Abstract: A semiconductor device or a hot electron transistor being constructed such that an InAs base layer is sandwiched between a GaSb emitter barrier layer and a GaInAsSb-system collector barrier layer, which results in preventing hot electrons of unnecessarily high energy from being injected into the collector and an avalanche current from being generated, thereby making it possible to improve the saturation characteristics of the device.

Abstract: A III-V semiconductor device is disclosed, which includes an emitter region, an emitter barrier region having such a barrier height as to substantially restrict a thermionic emission current as compared with a tunneling current and such a barrier width as to permit the tunneling current, a base region containing indium and having higher electron affinity than said emitter region and a collector barrier region having such a barrier height as to substantially prohibit a thermally distributed electron from overflowing and such a barrier width as to substantially prohibit the tunneling current.