Patents by Inventor Ichiro Honma

Ichiro Honma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8329584
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
  • Publication number: 20110230051
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Application
    Filed: June 2, 2011
    Publication date: September 22, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiyuki TAKEWAKI, Manabu IGUCHI, Daisuke OSHIDA, Hironori TOYOSHIMA, Masayuki HIROI, Takuji ONUMA, Hiroaki NANBA, Ichiro HONMA, Mieko HASEGAWA, Yasuaki TSUCHIYA, Toshiji TAIJI, Takaharu KUNUGI
  • Patent number: 7955980
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
  • Publication number: 20090305496
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Application
    Filed: August 18, 2009
    Publication date: December 10, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Toshiyuki TAKEWAKI, Manabu IGUCHI, Daisuke OSHIDA, Hironori TOYOSHIMA, Masayuki HIROI, Takuji ONUMA, Hiroaki NANBA, Ichiro HONMA, Mieko HASEGAWA, Yasuaki TSUCHIYA, Toshiji TAIJI, Takaharu KUNUGI
  • Patent number: 7601640
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
  • Publication number: 20080160750
    Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
    Type: Application
    Filed: December 10, 2007
    Publication date: July 3, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Toshiyuki TAKEWAKI, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takahara Kunugi
  • Publication number: 20040245643
    Abstract: A semiconductor device includes a first wiring layer section formed above a semiconductor substrate; and a second wiring layer section formed on the first wiring layer section. The latter includes a first interlayer insulating film; a plurality of first via-plugs formed in the first interlayer insulating film separated from each other by a first distance; and a plurality of first wiring lines formed on the plurality of first via-plugs in the first interlayer insulating film and connected with the plurality of first via-plugs. The second wiring layer section includes a second interlayer insulating film; a plurality of second via-plugs formed in the second interlayer insulating film, separated from each other by a second distance which is longer than the first distance; and a plurality of second wiring lines formed on the plurality of second via-plugs in the second interlayer insulating film and connected with the plurality of second via-plugs, respectively.
    Type: Application
    Filed: June 3, 2004
    Publication date: December 9, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Toshiyuki Takewaki, Noriaki Oda, Ichiro Honma
  • Patent number: 6568243
    Abstract: Surface irregularity of a semiconductor device is measured with high accuracy, without being affected by the material properties of a semiconductor film forming the surface. Surface irregularity is evaluated when the semiconductor device is fabricated. This is accomplished using a plate-like element, which has a contact surface brought into contact with the surface of a test specimen. The plate-like element is then moved across the surface of the test specimen by a driving mechanism. The driving mechanism moves either the plate-like element or the test specimen relative to the other. A force caused by the motion is detected, and converted into a parameter equivalent to the friction coefficient between the test specimen and the contact surface. From the friction coefficient, surface irregularity is determined.
    Type: Grant
    Filed: February 19, 1999
    Date of Patent: May 27, 2003
    Assignee: NEC Corporation
    Inventor: Ichiro Honma
  • Patent number: 6342714
    Abstract: A hemispherical grained (HSG) lower electrode, and its manufacturing method, are disclosed in which the yield is enhanced by suppressing the depletion due to insufficient diffusion of an impurity into the hemispherical grains (abbreviated also as HSGs) to reduce the deterioration in the capacity caused by the defect on the negative (lower) electrode side, and preventing the fracture of the HSGs. In a method of forming a capacitor composed of a polysilicon lower electrode, a dielectric film, and an upper electrode, the method of this invention includes at least a step of forming HSG silicon on the lower electrode, where each of its grains has a neck with decreased diameter on the side of the contact plane with the lower electrode, a step of depositing a silicon film covering the HSGs by filling the gaps between the lower electrode in the periphery of the necks and the HSGs while maintaining the rugged shape of the formed HSGs, a step of forming a dielectric film, and a step of forming an upper electrode.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: January 29, 2002
    Assignee: NEC Corporation
    Inventors: Toshiyuki Hirota, Ichiro Honma
  • Patent number: 6329268
    Abstract: In a method of manufacturing a semiconductor device that has an amorphous-silicon film onto which hemispherical grains are grown, a silicon wafer is cleaned at an elevated temperature using amnmonia hydrogen peroxide water solution, cleaned at an elevated temperature using chlorine hydrogen peroxide water solution, and then immersed in dilute hydrofluoric acid solution, after which it is rinsed with pure water, after which the amorphous-silicon film surface of the wafer is dried using isopropyl alcohol.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: December 11, 2001
    Assignee: NEC Corporation
    Inventors: Masaharu Nakamori, Ichiro Honma
  • Patent number: 6313004
    Abstract: After HSG-Si 15a is formed on the surface of a polycrystal silicon film 15, heat treatment is conducted on it using a phosphorus diffusion apparatus in an atmosphere of a mixture gas containing POCl3, O2, and N2 gases in such a situation that the O2/POCl3 mole ratio is adjusted into 0.2 through 1.5, thus diffusing phosphorus into the HSG-Si 15a. With this, it is possible to suppress the corrosion of silicon by the chlorine radicals and inhibit the accelerated oxidation of silicon, thus preventing the reduction of the HSG-Si 15a.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: November 6, 2001
    Assignee: NEC Corporation
    Inventor: Ichiro Honma
  • Patent number: 6221730
    Abstract: A fabrication method of a semiconductor device is provided, which makes it possible to introduce suitably a dopant into surface grains of a semiconductor layer at a comparatively low temperature. In the first step, a first semiconductor layer is formed over a semiconductor substrate through a first dielectric. In the second step, the first semiconductor layer is heat-treated to form semiconductor grains on a surface of the first semiconductor layer, thereby roughening the surface of the first semiconductor layer. The grains are made of a same material as that of the first semiconductor layer. In the third step, the first semiconductor layer with the semiconductor grains is heat-treated at a temperature of approximately 700° C. to 780° C. for a specific time in an atmosphere containing a gaseous dopant, thereby introducing the dopant into the semiconductor grains of the first semiconductor layer from the atmosphere.
    Type: Grant
    Filed: February 2, 1999
    Date of Patent: April 24, 2001
    Assignee: NEC Corporation
    Inventor: Ichiro Honma
  • Patent number: 5989969
    Abstract: A method of forming a silicon layer disclosed herein includes the steps of depositing an amorphous silicon layer on a substrate, irradiating a silane gas to the substrate, and performing an annealing process in a high vacuum or in an inert gas. The amorphous silicon layer is thereby converted into a silicon layer having an uneven surface caused by hemispherical or spherical silicon grains. The annealing process may be performed while irradiating a hydrogen gas or an oxidizing gas. In this case, such a silicon layer that has an even surface is formed.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: November 23, 1999
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Ichiro Honma
  • Patent number: 5972750
    Abstract: There are disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps, and its manufacturing method. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventors: Hiroki Shirai, Taishi Kubota, Ichiro Honma, Hirohito Watanabe, Haruhiko Ono, Takeshi Okazawa
  • Patent number: 5973355
    Abstract: There is disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventors: Hiroki Shirai, Taishi Kubota, Ichiro Honma, Hirohito Watanabe, Haruhiko Ono, Takeshi Okazawa
  • Patent number: 5910019
    Abstract: A method of forming a silicon layer disclosed herein includes the steps of depositing an amorphous silicon layer on a substrate, irradiating a silane gas to the substrate, and performing an annealing process in a high vacuum or in an inert gas. The amorphous silicon layer is thereby converted into a silicon layer having an uneven surface caused by hemispherical or spherical silicon grains. The annealing process may be performed while irradiating a hydrogen gas or an oxidizing gas. In this case, such a silicon layer that has an even surface is formed.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: June 8, 1999
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Ichiro Honma
  • Patent number: 5858837
    Abstract: A method of manufacturing a semiconductor memory device, comprising the steps of: forming a gate electrode with an insulating spacer, forming a first silicon oxide film by high-temperature chemical vapor deposition (CVD), forming n-type source/drain regions, forming a first insulating interlayer and forming a bit line; forming a second silicon oxide film by low-temperature CVD, forming a BPSG film, and annealing the second silicon oxide film and the BPSG film by first annealing to form a second insulating interlayer constituted by the stacked films; forming a third silicon oxide film by low-temperature CVD, and annealing the third silicon oxide film by second annealing; forming a node contact hole through the annealed third silicon oxide film, the second insulating interlayer, the first insulating interlayer, and the first silicon oxide film; forming an amorphous silicon film doped n-type at the time of the film formation, patterning the amorphous silicon film to form an amorphous silicon film pattern, and re
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: January 12, 1999
    Assignee: NEC Corporation
    Inventors: Takashi Sakoh, Ichiro Honma
  • Patent number: 5730034
    Abstract: A movable automatic bolt driving apparatus sequentially drives a plurality of bolts positioned substantially in line on flanges of elongated concrete molding frame segments for producing columnar concrete products. The apparatus has a vertically movable bolt driver unit and an air-cylinder unit. When the bolt driver unit drives a bolt in a state that the socket and the bolt are non-concentrically engaged with each other, the air-cylinder unit causes to properly reposition the bolt driver unit. At least a part of the bolt driver unit, which is normally disposed vertically, is pivotable with a horizontal pivotal axis orthogonal to the moving direction of the apparatus. The apparatus also has a flange follower for guiding the bolt driver unit. At least a part of the flange follower, which includes a roller having a vertical rotating axis, is pivotable about a vertical rotational axis.
    Type: Grant
    Filed: May 10, 1996
    Date of Patent: March 24, 1998
    Assignee: K.K. Joban Engineering
    Inventors: Ryoichi Hashimoto, Ichiro Honma, Nobuhiko Nishiwaki
  • Patent number: 4594267
    Abstract: A cobalt-containing magnetic iron oxide powder is provided by first coating a magnetic iron oxide base powder with a ferrous compound and then coating it with a cobalt compound. The cobalt-containing magnetic iron oxide powder provided is improved in stability of coercivity under aging and various other magnetic properties, and the magnetic tape produced by using the powder is also appreciably improved in stability of coercivity under aging as well as in various magnetic properties such as squareness, orientability and switching field distribution.
    Type: Grant
    Filed: March 25, 1985
    Date of Patent: June 10, 1986
    Assignee: Ishihara Sangyo Kaisha, Ltd.
    Inventors: Ichiro Honma, Masaharu Hirai, Masatoshi Amano, Nobusuke Takumi
  • Patent number: 4551327
    Abstract: An aqueous slurry of a magnetic iron oxide powder is mixed with a suspension prepared by neutralizing an aqueous ferrous salt solution with an alkali to form ferrous hydroxide and then adding an aqueous cobalt salt solution thereto, and the excess OH concentration of the mixed slurry is adjusted to 0.05 to 3 mol/l, thereby obtaining a cobalt-and ferrous iron-containing ferromagnetic iron oxide. The cobalt-and ferrous iron-containing ferromagnetic iron oxide is excellent in coercivity, distribution of coercivity and other magnetic properties, and the magnetic tape produced by using such iron oxide is also excellent in coercivity and switching field distribution.
    Type: Grant
    Filed: July 12, 1983
    Date of Patent: November 5, 1985
    Assignee: Ishihara Sangyo Kaishi, Limited
    Inventors: Ichiro Honma, Arata Koyama, Masatoshi Amano, Nobusuke Takumi