Patents by Inventor Ichiro Kasama
Ichiro Kasama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10824423Abstract: A reconfigurable arithmetic device includes a plurality of processor elements configured to perform first arithmetic processes corresponding to a first type of instruction and second arithmetic processes corresponding to a second type of instruction, a random-access memory (RAM), and a control unit. The first type of instruction is written into the RAM at a first address, data for the first type of instruction is written into the RAM at a second address, and data for the second type of instruction is written into the RAM at a third address. When the first type of instruction is written at the first address, the control unit decodes the first type of instruction and configures the processor elements to perform the first arithmetic processes. When data for the second type of instruction is written at the third address, the control unit configures the processor elements to perform the second arithmetic processes.Type: GrantFiled: September 28, 2015Date of Patent: November 3, 2020Assignee: Cypress Semiconductor CorporationInventors: Hiroshi Furukawa, Ichiro Kasama
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Patent number: 9720879Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.Type: GrantFiled: December 20, 2010Date of Patent: August 1, 2017Assignee: Cypress Semiconductor CorporationInventors: Shinichi Sutou, Ichiro Kasama, Kyoji Sato, Takashi Hanai, Kiyomitsu Katou, Takahiro Kubota, Junji Sahoda
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Publication number: 20160092213Abstract: A reconfigurable arithmetic device includes a plurality of processor elements configured to perform first arithmetic processes corresponding to a first type of instruction and second arithmetic processes corresponding to a second type of instruction, a random-access memory (RAM), and a control unit. The first type of instruction is written into the RAM at a first address, data for the first type of instruction is written into the RAM at a second address, and data for the second type of instruction is written into the RAM at a third address. When the first type of instruction is written at the first address, the control unit decodes the first type of instruction and configures the processor elements to perform the first arithmetic processes. When data for the second type of instruction is written at the third address, the control unit configures the processor elements to perform the second arithmetic processes.Type: ApplicationFiled: September 28, 2015Publication date: March 31, 2016Inventors: Hiroshi FURUKAWA, Ichiro Kasama
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Patent number: 9146896Abstract: A computer system that includes a central processing unit, a random-access-memory interface, a random-access memory whose addresses are allocated in an address space of the random-access-memory interface, and a reconfigurable arithmetic device is described herein. The reconfigurable arithmetic device includes input terminals, output terminals, a network of plurality of processor elements, a built-in random-access memory, a control unit, an inter-processor-element network and a configuration-data memory. In accordance with configuration on data from the configuration-data memory, the inter processor-element network is capable of changing the connection state of the input terminals and the output terminals to input ports and output ports of the plurality of processor elements, and the arithmetic function of the reconfigurable arithmetic device is capable of being dynamically changed.Type: GrantFiled: June 7, 2010Date of Patent: September 29, 2015Assignee: Cypress Semiconductor CorporationInventors: Hiroshi Furukawa, Ichiro Kasama
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Patent number: 8150949Abstract: A reconfigurable computing apparatus includes plural computing element networks respectively formed of computing elements of an identical bit width, the bit width of each of the computing element networks differing according to computing element network; a bit width converting element that converts bit widths between the computing element networks; a control signal-dedicated network that is formed of computing elements, is reconfigurable, and controls each of the computing element networks; and a sequencer that controls a timing at which circuit configurations are switched with respect to the computing element networks, the control signal-dedicated network, and the bit width converting element.Type: GrantFiled: September 2, 2009Date of Patent: April 3, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Ichiro Kasama
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Publication number: 20110246747Abstract: A reconfigurable circuit includes a data execution unit including a plurality of execution elements, each of which performs execution with respect to plural data upon the plural data being all in a valid state, and holds valid-state output data indicative of a result of the execution at an output node while all the plural data are in the valid state, a data selecting unit configured to connect between the execution elements in a reconfigurable manner, and a data input unit configured to supply input data to a series of execution elements to perform a series of executions, wherein a valid or invalid state of given data is specified by a valid signal accompanying and forming a pair with the given data, and the input data supplied from the data input unit to the data execution unit are fixed to valid-state constant data while the series of executions are performed.Type: ApplicationFiled: March 28, 2011Publication date: October 6, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Takashi HANAI, Kiyomitsu Katou, Takahiro Kubota, Junji Sahoda, Ichiro Kasama, Kyoji Sato, Shinichi Sutou
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Publication number: 20110185152Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.Type: ApplicationFiled: December 20, 2010Publication date: July 28, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinichi Sutou, Ichiro Kasama, Kyoji Sato, Takashi Hanai, Kiyomitsu Katou, Takahiro Kubota, Junji Sahoda
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Patent number: 7908453Abstract: A semiconductor device includes a plurality of memories, a sequencer which outputs configuration information, and a memory reconfiguring circuit which reconfigures the memory area in accordance with the configuration information supplied from the sequencer. Since the memory reconfiguring circuit dynamically changes the allocation of the memories, it is possible to reconfigure the memory configuration and freely change the memory size in accordance with the purpose of use.Type: GrantFiled: June 28, 2005Date of Patent: March 15, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tetsuo Kawano, Hiroshi Furukawa, Ichiro Kasama, Kazuaki Imafuku, Toshiaki Suzuki, Miyoshi Saito
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Publication number: 20100332795Abstract: A computer system includes a central processing unit, a random-access-memory interface, a random-access memory in which addresses are allocated in an address space of the random-access-memory interface and a reconfigurable arithmetic device whose arithmetic function is capable of being dynamically changed in accordance with configuration data. The reconfigurable arithmetic device includes input terminals, output terminals, a plurality of processor elements that perform individual arithmetic processes in synchronization with a clock, an inter-processor-element network which connects the input terminals and the output terminals to input ports and output ports of the plurality of processor elements, a random-access memory built into the reconfigurable arithmetic device and a control unit that sets the plurality of processor elements and the inter-processor-element network.Type: ApplicationFiled: June 7, 2010Publication date: December 30, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hiroshi FURUKAWA, Ichiro Kasama
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Patent number: 7822888Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.Type: GrantFiled: October 26, 2004Date of Patent: October 26, 2010Assignee: Fujitsu LimitedInventors: Miyoshi Saito, Hisanori Fujisawa, Ichiro Kasama, Tetsuo Kawano, Kazuaki Imafuku, Hiroshi Furukawa, Shiro Uriu, Mitsuharu Wakayoshi
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Patent number: 7783693Abstract: A reconfigurable circuit is provided, which includes a first arithmetic unit that performs addition or subtraction of a first input data and a second input data and outputs output data, and a first selector that selects an output data of the first arithmetic unit or a third input data and outputs the selected one as the first input data to the first arithmetic unit.Type: GrantFiled: May 31, 2006Date of Patent: August 24, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Ichiro Kasama, Masato Miyake
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Patent number: 7774580Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.Type: GrantFiled: March 11, 2005Date of Patent: August 10, 2010Assignee: Fujitsu LimitedInventors: Miyoshi Saito, Hisanori Fujisawa, Hideki Yoshizawa, Tetsu Tanizawa, Ichiro Kasama, Tetsuo Kawano, Kazuaki Imafuku, Hiroshi Furukawa, Shiro Uriu, Mitsuharu Wakayoshi
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Publication number: 20090327461Abstract: A reconfigurable computing apparatus includes plural computing element networks respectively formed of computing elements of an identical bit width, the bit width of each of the computing element networks differing according to computing element network; a bit width converting element that converts bit widths between the computing element networks; a control signal-dedicated network that is formed of computing elements, is reconfigurable, and controls each of the computing element networks; and a sequencer that controls a timing at which circuit configurations are switched with respect to the computing element networks, the control signal-dedicated network, and the bit width converting element.Type: ApplicationFiled: September 2, 2009Publication date: December 31, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Ichiro KASAMA
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Patent number: 7580963Abstract: A semiconductor device includes a configuration memory for storing configuration data, an arithmetic unit whose circuit configuration can be reconfigured in accordance with the configuration data, and a fixed value memory for storing fixed value data to be supplied to the arithmetic unit. Since the configuration data and fixed value data to be supplied to the arithmetic unit are stored in the different memories, no data area for storing the fixed value data need be set in the configuration memory. This makes it possible to supply a predetermined fixed value to the arithmetic unit by storing only information for reading out fixed value data from the fixed value memory.Type: GrantFiled: January 14, 2005Date of Patent: August 25, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tetsuo Kawano, Hiroshi Furukawa, Ichiro Kasama, Kazuaki Imafuku, Toshiaki Suzuki
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Publication number: 20070220236Abstract: A reconfigurable computing device includes computing unit groups each of which includes at least one computing unit; a bus network that is reconfigurable and that uses arbitrary output data of the computing unit groups as arbitrary input data for the computing unit groups; a sequencer that outputs address information for controlling circuit configurations of the computing unit groups and switch-timing signals; and a configuration output unit that makes circuits of the computing unit groups reconfigurable for each of the computing unit groups, based on the address information and the switch-timing signals.Type: ApplicationFiled: July 18, 2006Publication date: September 20, 2007Applicant: FUJITSU LIMITEDInventor: Ichiro Kasama
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Publication number: 20070198619Abstract: A reconfigurable circuit is provided, which includes a first arithmetic unit that performs addition or subtraction of a first input data and a second input data and outputs output data, and a first selector that selects an output data of the first arithmetic unit or a third input data and outputs the selected one as the first input data to the first arithmetic unit.Type: ApplicationFiled: May 31, 2006Publication date: August 23, 2007Applicant: FUJITSU LIMITEDInventors: Ichiro Kasama, Masato Miyake
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Publication number: 20070150707Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.Type: ApplicationFiled: March 2, 2007Publication date: June 28, 2007Applicant: FUJITSU LIMITEDInventors: Shiro URIU, Mitsuharu Wakayoshi, Tetsuo Kawano, Hiroshi Furukawa, Ichiro Kasama, Kazuaki Imafuku, Toshiaki Suzuki
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Patent number: 7194610Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.Type: GrantFiled: February 23, 2005Date of Patent: March 20, 2007Assignee: Fujitsu LimitedInventors: Shiro Uriu, Mitsuharu Wakayoshi, Tetsuo Kawano, Hiroshi Furukawa, Ichiro Kasama, Kazuaki Imafuku, Toshiaki Suzuki
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Publication number: 20070033369Abstract: A reconfigurable integrated circuit device which is dynamically constructed to be an arbitrary operation status based on a configuration data, has a plurality of clusters including operation processor elements, a memory processor element, and an inter-processor element switch group for connecting the elements in an arbitrary status; an inter-cluster switch group for constructing data paths between the clusters in an arbitrary status; and an external memory bus. A direct memory access control section, for executing the data transfer between the memory processor element and the external memory by direct memory access responding to an access request from the memory processor elements of the plurality of clusters, is further provided.Type: ApplicationFiled: January 27, 2006Publication date: February 8, 2007Inventors: Ichiro Kasama, Toru Tsuruta, Masaru Nishida
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Publication number: 20060010306Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.Type: ApplicationFiled: March 11, 2005Publication date: January 12, 2006Inventors: Miyoshi Saito, Hisanori Fujisawa, Hideki Yoshizawa, Tetsu Tanizawa, Ichiro Kasama, Tetsuo Kawano, Kazuaki Imafuku, Hiroshi Furukawa, Shiro Uriu, Mitsuharu Wakayoshi