Abstract: A method of manufacturing a semiconductor device, includes: preparing a support substrate having a peeling layer formed on a main surface side; partially forming a wiring layer above the peeling layer; arranging a semiconductor chip on the support substrate so that a pad of the semiconductor chip is electrically connected to the wiring layer; forming an encapsulating layer that encapsulates at least a part of the wiring layer and the semiconductor chip and is in contact with the peeling layer or a layer above the peeling layer so as to form an intermediate laminated body including the semiconductor chip, the wiring layer, and the encapsulating layer on the support substrate; cutting a peripheral portion of the support substrate after forming the intermediate laminated body; and mechanically peeling the intermediate laminated body from the support substrate with the peripheral portion cut away, with the peeling layer being as a boundary.

Abstract: A product image representing an upper body of a vehicle having a reference shape and a shift index segment image linearly extending from each of a plurality of designated virtual space locations of the product image in each of a plurality of directions of virtual spaces are displayed. Each of the plurality of designated virtual space locations corresponds to each of a plurality of designated real space locations of the upper body of the vehicle having the reference shape. A length of the shift index segment image represents a quantity of a virtual space position shift amount. The “virtual space position shift amount” corresponds to a real space position shift amount in a direction of a real space at a designated real space location of the upper body based on reference data of the upper body.

Abstract: An accuracy evaluation apparatus evaluates accuracy of coupling portion where first component having first coupling surface and second component having second coupling surface are coupled to each other. The apparatus includes: display unit; and CPU and memory. The CPU is configured to perform: acquiring design data and measurement data of the components; calculating error between design reference point on the coupling surfaces in the design data and reference points on the coupling surfaces corresponding to the design reference point in the measurement data; and calculating interference degree at the design reference point when coupling components based on the error. The display unit displays design model of the components based on the design data and superimposes indicator representing the interference degree on the design model at the design reference point.

Abstract: A method of manufacturing a semiconductor device, includes: preparing a support substrate having a peeling layer formed on a main surface side; partially forming a wiring layer above the peeling layer; arranging a semiconductor chip on the support substrate so that a pad of the semiconductor chip is electrically connected to the wiring layer; forming an encapsulating layer that encapsulates at least a part of the wiring layer and the semiconductor chip and is in contact with the peeling layer or a layer above the peeling layer so as to form an intermediate laminated body including the semiconductor chip, the wiring layer, and the encapsulating layer on the support substrate; cutting a peripheral portion of the support substrate after forming the intermediate laminated body; and mechanically peeling the intermediate laminated body from the support substrate with the peripheral portion cut away, with the peeling layer being as a boundary.

Abstract: A product image representing an upper body of a vehicle having a reference shape and a shift index segment image linearly extending from each of a plurality of designated virtual space locations of the product image in each of a plurality of directions of virtual spaces are displayed. Each of the plurality of designated virtual space locations corresponds to each of a plurality of designated real space locations of the upper body of the vehicle having the reference shape. A length of the shift index segment image represents a quantity of a virtual space position shift amount. The “virtual space position shift amount” corresponds to a real space position shift amount in a direction of a real space at a designated real space location of the upper body based on reference data of the upper body.

Abstract: A vibration-sensor-integrated vibration exciter 4 has a chassis 21, an excitation unit 22, a magnet 23, a yoke 24, a vibration sensor 25, a fixed plate 26, a moving plate 27, coil springs 28a to 28d, a retaining plate 29, and a crisscross plate 30. Shafts 31a to 31d are fixed to the fixed plate 26. The excitation unit 22 is fixed to the crisscross plate 30. Four vibration-proof rubber members 32a to 32d are installed to the crisscross plate 30 at 90-degree pitches with same radius centering on the excitation axis of the fixed excitation unit 22. The crisscross plate 30 is installed to the retaining plate 29 through the vibration-proof rubber members 32a to 32d. A vibration applied to the chassis 21 is absorbed by the vibration-proof rubber members 32a to 32d, to prevent the yoke 24 from being dislocated in lateral direction due to the vibration.

Abstract: A vibration-sensor-integrated vibration exciter 4 has a chassis 21, an excitation unit 22, a magnet 23, a yoke 24, a vibration sensor 25, a fixed plate 26, a moving plate 27, coil springs 28a to 28d, a retaining plate 29, and a crisscross plate 30. Shafts 31a to 31d are fixed to the fixed plate 26. The excitation unit 22 is fixed to the crisscross plate 30. Four vibration-proof rubber members 32a to 32d are installed to the crisscross plate 30 at 90-degree pitches with same radius centering on the excitation axis of the fixed excitation unit 22. The crisscross plate 30 is installed to the retaining plate 29 through the vibration-proof rubber members 32a to 32d. A vibration applied to the chassis 21 is absorbed by the vibration-proof rubber members 32a to 32d, to prevent the yoke 24 from being dislocated in lateral direction due to the vibration.

Abstract: A method of manufacturing a semiconductor device, including steps of: (a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon; (b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face; (c) dividing the wafer into multiple chip bodies concurrently with or after step (b); (d) bonding multiple reinforcing layers to second main faces of the respective chip bodies after step (c); and (e) removing the support plate after step (d).

Abstract: A method of manufacturing a semiconductor device, including steps of: (a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon; (b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face; (c) dividing the wafer into multiple chip bodies concurrently with or after step (b); (d) bonding multiple reinforcing layers to second main faces of the respective chip bodies after step (c); and (e) removing the support plate after step (d).

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes preparing a semiconductor substrate includes a connection pad to electrically connect to a circuit element formed on a main surface, or a rewiring line connected to the connection pad, forming an insulating photosensitive resin film on the substrate with the exclusion of at least an edge portion of the substrate by inkjet, patterning the photosensitive resin film by photolithography, and forming a rewiring line, UBM or an electrode for external connection on the substrate on which the patterned photosensitive resin film is formed.

Abstract: A manufacturing method of a semiconductor device includes thermally curing a thermosetting resin material layer formed on a semiconductor wafer at a first temperature of 100° C. to 200° C. to form a protective film, preheating the semiconductor wafer having the protective film formed therein at a second temperature and removing water on the surface of the protective film, bias sputtering on the preheated semiconductor wafer, then controlling the temperature of the semiconductor wafer to a third temperature of not more than 200° C., and sputtering a material selected from the group consisting of Ti, TiW, Ta, and a conductive Ti compound to form a first conductive underlayer on the protective film.

Abstract: A panel inspection apparatus includes a resonant frequency extracting unit for extracting a plurality of resonant frequencies of a panel, a resonant frequency selecting unit for selecting a combination of resonant frequencies consisting of two resonant frequencies A and B with different vibration propagation paths among the extracted plurality of resonant frequencies, a non-defective range generating unit for generating a non-defective range on a coordinate system in which resonant frequencies A and B are taken on coordinate axes by statistically processing a set of the resonant frequencies A and B selected for each of a plurality of non-defective panels determined as non-defective in advance, and a panel quality determining unit for determining whether the quality of the panel to be inspected is good based on comparison between resonant frequencies A and B selected for the panel to be inspected and the non-defective range generated by the non-defective range generating unit.

Abstract: A panel inspection apparatus includes a resonant frequency extracting unit for extracting a plurality of resonant frequencies of a panel, a resonant frequency selecting unit for selecting a combination of resonant frequencies consisting of two resonant frequencies A and B with different vibration propagation paths among the extracted plurality of resonant frequencies, a non-defective range generating unit for generating a non-defective range on a coordinate system in which resonant frequencies A and B are taken on coordinate axes by statistically processing a set of the resonant frequencies A and B selected for each of a plurality of non-defective panels determined as non-defective in advance, and a panel quality determining unit for determining whether the quality of the panel to be inspected is good based on comparison between resonant frequencies A and B selected for the panel to be inspected and the non-defective range generated by the non-defective range generating unit.

Abstract: A 2-input AND gate is inserted between an output terminal of a scan flipflop with an input selectable gate and a logic output signal line. The 2-input AND gate is controlled by a scan-enable signal line, and has a role to fix the transition of the output signal of the scan flipflop.

Abstract: A semiconductor integrated circuit includes: a first p-channel FET having a gate controlled by a first input and having a source-drain path connected between a first operating potential point and a first node; a first n-channel FET having a gate controlled by a second input and having a source-drain path connected between the first node and a second node; a second n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a second operating potential point; a third n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a third operating potential point; a second p-channel FET having a gate controlled by the first input and having a source-drain path connected between a third node and a fourth node; a third p-channel FET having a gate controlled by the fourth node and having a source-drain path connected between the first operating potential point and the third node; a fourt

Abstract: A 2-input AND gate is inserted between an output terminal of a scan flipflop with an input selectable gate and a logic output signal line. The 2-input AND gate is controlled by a scan-enable signal line, and has a role to fix the transition of the output signal of the scan flipflop.

Abstract: In order to provide a semiconductor integrated circuit in which power consumption due to a leakage current in an active mode can be suppressed and which can operate at a high speed, the semiconductor integrated circuit includes: a first p-channel FET having a gate controlled by a first input and having a source-drain path connected between a first operating potential point and a first node; a first n-channel FET having a gate controlled by a second input and having a source-drain path connected between the first node and a second node; a second n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a second operating potential point; a third n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a third operating potential point; a second p-channel FET having a gate controlled by the first input and having a source-drain path connected between a third node and a fourth

Abstract: In order to provide a semiconductor integrated circuit in which power consumption due to a leakage current in an active mode can be suppressed and which can operate at a high speed, the semiconductor integrated circuit includes: a first p-channel FET having a gate controlled by a first input and having a source-drain path connected between a first operating potential point and a first node; a first n-channel FET having a gate controlled by a second input and having a source-drain path connected between the first node and a second node; a second n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a second operating potential point; a third n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a third operating potential point; a second p-channel FET having a gate controlled by the first input and having a source-drain path connected between a third node and a fourth

Abstract: A phototransistor having a non-linear light vs. conductivity characteristics and an organic electroluminescent layer are sandwiched by a pair of electrodes, a predetermined voltage is applied to the pair of electrodes, and address light is irradiated on a phototransistor to let a current flow in the phototransistor, thus causing the electroluminescent layer to emit light. It is therefore possible to drive the device to present crosstalk-free gradation display with a high contrast ratio.