Abstract: A block infinite impulse response (IIR) processor has a first input register storing data of the block length "L" and capable of shifting the stored data by an integer times the data word length, a first coefficient register file, a second input register, a second coefficient register file, a third input register, a third coefficient register file, a register, a shift register, an accumulator and a multiply-and-accumulate unit for multiplying respective data blocks in the register by a least significant word in the shift register, and for adding the result of the multiplication to a value of the accumulator, for executing a parallel operation of "L" multiply-and-accumulate operations.

Abstract: An 8.times.8 two-dimensional discrete inverse cosine transform circuit includes two row arithmetic sections each of which implement an 8-point one-dimensional inverse discrete cosine transform in a row direction, a replacement section which replaces the arithmetic results of the row arithmetic sections with replacement data, and two column arithmetic sections each of which receive parts of the replacement data from the replacement section and implement an 8-point one-dimensional inverse discrete cosine transform in a column direction. Each of the arithmetic sections include a 16-bit four parallel adder and subtracter and a 16-bit four parallel multiply-accumulate unit with polarity symmetric rounding function.

Abstract: The invention provides a high speed two-dimensional discrete cosine transform circuit which can reduce the number of addition operations for rounding to one time. The two-dimensional IDCT circuit calculates M.times.N-point two-dimensional inverse discrete cosine transforms wherein M.times.N is equal to 2.sup.2n, and includes an M.times.N two-dimensional IDCT operator for calculating two-dimensional inverse discrete cosine transforms as matrix vector products of a transform matrix of MN rows and MN columns and MNth-order input vectors, a shift operator for shifting results of the calculation of the M.times.N two-dimensional IDCT operator rightwardly, and an adder for adding 2.sup.n-2 to a discrete cosine coefficient from among discrete cosine transform coefficients to be inputted to the M.times.N two-dimensional IDCT operator. An output signal of the shift operator is outputted as a circuit output signal of the two-dimensional IDCT circuit.

Abstract: First to ninth determining units that receive input data of first to ninth tensor product calculating units are disposed. The first to ninth determining units determine whether or not the received data have non-zero data and supply the determined results to the relevant tensor product calculating units. When the first to ninth determining units have determined that all of the received data are zero data, the first to ninth tensor product calculating units do not perform tensor product calculations.

Abstract: A two-dimensional discrete cosine transformation circuit performs 8 points.times.8 points two-dimensional discrete cosine transformation. The circuit comprises a first stage calculation circuit, a second stage calculation circuit, and a third stage calculation circuit. The first stage calculation circuit includes sixteen two-dimensional butterfly computing circuits. The second stage calculation circuit includes four two-dimensional butterfly computing circuits, eight first one-dimensional butterfly computing circuits and eight second one-dimensional butterfly computing circuits. The third stage calculation circuit includes nine tensor product computing elements.

Abstract: In a motion estimating system, the sum of square values of picture element values of a current block is calculated in a current block square sum calculator and stored in a storage unit. The inner product between the current block and each of some or all of reference blocks in a reference area is multiplied by -2 every reference block, and stored in a memory. Further, the sum of square values of picture elements of some or all of the reference blocks in the reference area is calculated every reference block, and stored a memory. The square sum value of the current block, the product value of -2 and the inner product between the current block and the reference block which corresponds to a motion vector to be searched, and the square sum value of the reference block are added in an adder to set the addition result as an error power value. Finally, the minimum value of the error power is detected to estimate the optimum motion vector.

Abstract: A program control circuit which comprises a register for holding the repetition number of a program operation to be repeated. The control circuit further comprises a counter for receiving the content of the register and adapted to be decremented in response to each execution of the program operation to be repeated. A memory stores a sequence of instructions. A controller transfers an instruction read from the memory without modification in a normal condition and modifies the instruction read from the memory into a no-operation instruction when the contents of the counter reaches a predetermined contents.

Abstract: A for controlling a includes circuit a register for holding the repetition number of a program operation to be repeated, a counter receiving the content of the register and adapted to decrement in response with each execution of the program operation to be repeated, a memory for storing a sequence of instructions, and a controller for receiving an instruction read from the memory modification in a normal condition and to convert the received instruction into a no-operation instruction when the content of the counter becomes a predetermined content.

Abstract: In a signal processor for processing zeroth through (N-1)-th input signal elements into zeroth through (N-1)-th output signal elements, the input elements are initially stored, as memorized data, in respective memory addresses of a memory arrangement (11, 12) by a memory accessing arrangement which comprises a first address calculating arrangement (311, 321) for calculating a first address for the memory addresses. A distance indicating arrangement (312, 322) is for indicating an address distance from the first address among the memory addresses. By using the first address and the address distance a second address is calculated by a second address calculating arrangement (313, 323). A pair of stored data are read from the first and the second addresses as a pair of read data.

Abstract: An apparatus for conversion between IEEE standard floating-point numbers and two's complement floating-point numbers provides a specialized circuit for high-speed two-way conversion between the IEEE standard floating-point format and the two's complement floating-point format. The apparatus eliminates problems that occur when the conversion is performed by a computer program.

Abstract: A digital signal processing circuit reduces the occurrence of overflow conditions during successive arithmetic operations. The product output of a multiplication circuit is shifted by a barrel shifter to round off a predetermined number of least significant bits, thereby reducing the occurrence of an overflow condition when the successive product outputs of the multiplication circuit are summed by an arithmetic logic unit (ALU) to produce a summed output. The summed output is then shifted toward the most significant bit by a predetermined number before an output signal is generated. An overflow detection and correction circuit is provided in the event of an overflow condition occurring either to the ALU or the barrel shifter.

Abstract: A multi-digit counter circuit performs both successive data production function and non-successive data production. Successive data is produced by an increment or decrement operation according to a first carry (borrow) signal. Non-successive data is produced by a control circuit which applies a second carry (borrow) signal independently of the first carry (borrow) signal to an arbitrary selected digit or digits. The arbitrary digit is designated according to the distance between the preceding data and the following data to be produced.

Abstract: A double precision multiplyer for performing the multiplication of two double precision data using a 2's complement single precision multiplier. The 2n-1 bit double precision data is divided into one single precision data formed by taking the upper n bits of the double precision data and another single precision data formed by adding a "0" bit before the most significant bit of the remaining n-1 bits of the double precision data. Apparatus for performing the double precision multiplication thereby eliminates the necessity of discriminating the sign bit and enhances the speed of the double precision multiplication.

Abstract: In an APDCM decoding circuit, an adaptive inverse quantizer which forms a quantized coded signal, produces a residual signal and upper and lower limits thereof. An adaptive prediction circuit uses the residual signal to predict a quantization, which is added to the other signals. The added residual is converted into a nonlinear encoded PCM for output. However the output is PCM linearized and compared to the added upper and lower limits to determine if the output should be incremented or decremented.