Patents by Inventor Ichiro Kyushima

Ichiro Kyushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080271001
    Abstract: In programming in high-level language, a method of generating a program supporting external specifications for generating secure codes having high tamper-resistance and automatically generating an executable program having tamper-resistance with regard to a portion designated by a user is provided. A syntax analysis step, an intermediate representation generation step, a register allocation step, an optimization processing step, an assembly language generation step, a machine language generation step and a machine language program linkage step are executed. And between finish of reading of the source program and generating the executable program, a tamper-resistant code insertion step of automatically generating a code having tamper-resistance coping with unjust analysis of an operation content of the executable program is executed to the source program, the intermediate representation, the assembly language program or the machine language program based on an instruction of a user.
    Type: Application
    Filed: September 11, 2007
    Publication date: October 30, 2008
    Inventors: Yo Nonomura, Shunsuke Ota, Takashi Endo, Takashi Tsukamoto, Ichiro Kyushima, Hiromi Nagayama, Kenichi Hirane, Yoshiyuki Amanuma
  • Patent number: 7313787
    Abstract: Different optimizing methods are applied in response to such a memory hierarchy to which a program mainly accesses when the program is executed. A memory hierarchy to which a program mainly accesses is designated by a user with employment of either a compiler option designation or a designation statement contained in the program. In a compiler, a memory hierarchy designation is analyzed, and an optimizing process according to the designated memory hierarchy is carried out.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: December 25, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Keiko Motokawa, Ichiro Kyushima, Shinichi Ito
  • Publication number: 20040199907
    Abstract: Different optimizing methods are applied in response to such a memory hierarchy to which a program mainly accesses when the program is executed. A memory hierarchy to which a program mainly accesses is designated by a user with employment of either a compiler option designation or a designation statement contained in the program. In a compiler, a memory hierarchy designation is analyzed, and an optimizing process according to the designated memory hierarchy is carried out.
    Type: Application
    Filed: September 19, 2003
    Publication date: October 7, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Keiko Motokawa, Ichiro Kyushima, Shinichi Ito
  • Publication number: 20040154007
    Abstract: A translator system for translating source programs into machine language programs in an electronic computer system. An object program common to a plurality of different machine types of computers are generated while implementing execution performance equivalent to object programs inherent to the computers. A compiler translates a source program into an abstract object program including an abstract machine instruction sequence and indication concerning allocation of abstract registers. An installer converts the abstract object program into a machine language program of target computer on the basis of executable computer specification information including register usage indication and machine instruction selecting rules.
    Type: Application
    Filed: January 23, 2004
    Publication date: August 5, 2004
    Inventors: Shinobu Koizumi, Ichiro Kyushima, Tan Watanabe, Toshiaki Kohno, Singi Domen
  • Publication number: 20020026633
    Abstract: A translator system for translating source programs into machine language programs in an electronic computer system. An object program common to a plurality of different machine types of computers are generated while implementing execution performance equivalent to object programs inherent to the computers. A compiler translates a source program into an abstract object program including an abstract machine instruction sequence and indication concerning allocation of abstract registers. An installer converts the abstract object program into a machine language program of target computer on the basis of executable computer specification information including register usage indication and machine instruction selecting rules.
    Type: Application
    Filed: May 18, 1998
    Publication date: February 28, 2002
    Inventors: SHINOBU KOIZUMI, ICHIRO KYUSHIMA, TAN WATANABE, TOSHIAKI KOHNO, SINGI DOMEN
  • Patent number: 6343373
    Abstract: A translator system for translating source programs into machine language programs in an electronic computer system. An object program common to a plurality of different machine types of computers are generated while implementing execution performance equivalent to object programs inherent to the computers. A compiler translates a source program into an abstract object program including an abstract machine instruction sequence and indication concerning allocation of abstract registers. An installer converts the abstract object program into a machine language program of target computer on the basis of executable computer specification information including register usage indication and machine instruction selecting rules.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: January 29, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Shinobu Koizumi, Ichiro Kyushima, Tan Watanabe, Toshiaki Kohno, Singi Domen
  • Publication number: 20010044931
    Abstract: Based on a repetitively executed program fragment like a loop in a source program, at least two patterns of object codes are generated which include object codes (a) using a speculative instruction and a speculative check instruction and an object codes (b) not using the speculative instruction and the speculative check instruction. Other object codes are generated that perform control transfer so that after the number of times a speculation failure is detected by the speculation check during the execution of the codes (a) satisfies a predetermined condition, the codes (b) are used for the subsequent repetitive execution.
    Type: Application
    Filed: May 15, 2001
    Publication date: November 22, 2001
    Inventors: Ichiro Kyushima, Hiroyasu Nishiyama
  • Patent number: 6055627
    Abstract: Particular portions of a program is determined to execute repeatedly. Array references accessed in a loop are classified to groups of equal values on the basis of reference to the same array. Of the groups, the ones for which an array transposition can use a batch load or store instruction are selected. An array corresponding to the selected groups is transposed to generate an intermediate language for copying. Reference to the elements of the array before the transposition is changed to reference to the transposition array. This makes it possible to convert the loop so that a single instruction can be used for a processor which can load into a register two data having consecutive addresses in a memory with use of the instruction.
    Type: Grant
    Filed: June 16, 1993
    Date of Patent: April 25, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Kyushima, Masahiro Kainaga
  • Patent number: 5586323
    Abstract: A translator system for translating source programs into machine language programs in an electronic computer system. An object program common to a plurality of different machine types of computers are generated while implementing execution performance equivalent to object programs inherent to the computers. A compiler translates a source program into an abstract object program including an abstract machine instruction sequence and indication concerning allocation of abstract registers. An installer converts the abstract object program into a machine language program of target computer on the basis of executable computer specification information including register usage indication and machine instruction selecting rules.
    Type: Grant
    Filed: April 23, 1992
    Date of Patent: December 17, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Shinobu Koizumi, Ichiro Kyushima, Tan Watanabe, Toshiaki Kohno, Singi Domen
  • Patent number: 5546559
    Abstract: A control system for a cache provided between a central processing unit and a main memory. The control system includes a plurality of entries each having a data area and a control information area. A reuse information field in the control information area is set at the same time as a load/store instruction from the central processing unit. When the central processing unit issues an access instruction to desired data in the main memory, an entry storing the desired data to be accessed is searched from a plurality of entries of the cache. If the desired data is not present in any of the plurality of entries, the desired data is read from the main memory. Then, an empty entry is searched from the plurality of entries. If there is no empty entry, an entry is selected which is not set with the reuse information in the control information area of the entry, the reuse information instructing to preferentially maintaining the data in the data field of the entry.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: August 13, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Kyushima, Masahiro Kainaga
  • Patent number: 4989145
    Abstract: A system for analyzing syntax in a language processing system includes a memory which stores preselected indentation rules associated with a source code level language. A lexical analyzer reads a sequence of input symbols from the source code, and divides them into tokens, which tokens form sequences of symbols having a collective meaning. A syntax analyzer receives information from the tokens and compares the same to indentation rules stored in the memory. Source code correction, suggested source code correction, or warnings indicative of improper identation are selectively generated in accordance with an output of the syntax analyzer.
    Type: Grant
    Filed: September 18, 1989
    Date of Patent: January 29, 1991
    Assignee: Hitachi, Ltd.
    Inventor: Ichiro Kyushima