Abstract: A vapor phase growth method of an embodiment is a vapor phase growth method using a vapor phase growth apparatus including a reactor, an exhaust pump, a pressure control valve, and an exhaust pipe. The vapor phase growth method includes: loading a first substrate into the reactor, heating the first substrate, supplying a process gas, and forming a silicon carbide film on a surface of the first substrate and depositing a by-product containing carbon in the first portion or the second portion by adjusting a pressure in the reactor by controlling the pressure control valve; unloading the first substrate from the reactor; removing the by-product by supplying a gas including a gas containing fluorine to the exhaust pipe by controlling a pressure in the exhaust pipe; and then loading a second substrate into the reactor to form a silicon carbide film on a surface of the second substrate.

Abstract: A SiC epitaxial growth apparatus according to an embodiment includes: a chamber into which a process gas at least containing silicon and carbon is introduced and housing a substrate to undergo epitaxial growth with the process gas; piping that discharges a gas containing a byproduct generated through epitaxial growth from the chamber; and a valve for pressure control in a middle of the piping. The valve has a flow inlet into which the gas flows from an upstream portion of the piping that causes the chamber and the valve to connect, and a flow outlet that allows the gas to flow out to a downstream portion of the piping that connects with the upstream portion via the valve. a part of the downstream portion is at a position lower than the flow outlet. The apparatus comprises a trap part being capable of collecting the byproduct at the downstream portion.

Abstract: According to an embodiment, a semiconductor device includes a silicon substrate, a device layer, and a lower layer. The device layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract: According to an embodiment, a semiconductor device includes a silicon substrate, a semiconductor layer, and a lower layer. The semiconductor layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a pattern portion and a flat portion on a substrate, the pattern portion including plural patterns, and the flat portion having a flat surface at a position lower than upper surfaces of the patterns. The method further includes transferring a first film on the substrate to continuously form the first film on the upper surfaces of the patterns and on the flat surface of the flat portion and to form a first air gap between the patterns.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming, on a semiconductor substrate, a sacrificial semiconductor pillar having a pillar-like shape extending in a first direction perpendicular to a main surface of the semiconductor substrate, and being formed of a first semiconductor material. The method further includes forming, around the sacrificial semiconductor pillar, a channel semiconductor layer having a tube-like shape extending in the first direction, and being formed of a second semiconductor material different from the first semiconductor material. The method further includes removing the sacrificial semiconductor pillar after the channel semiconductor layer is formed. The channel semiconductor layer is formed on electrode layers via an insulator, the electrode layers being formed on the semiconductor substrate.

Abstract: A memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a pattern portion and a flat portion on a substrate, the pattern portion including plural patterns, and the flat portion having a flat surface at a position lower than upper surfaces of the patterns. The method further includes transferring a first film on the substrate to continuously form the first film on the upper surfaces of the patterns and on the flat surface of the flat portion and to form a first air gap between the patterns.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device. The method includes introducing an inert gas and a material gas into a predetermined space, applying a voltage to generate plasma in the space after introducing the inert gas and the material gas so as to form a semiconductor layer on a substrate, introducing an oxidation-reduction gas in the predetermined space after the voltage is applied, and stopping the introduction of the material gas, the inert gas, and the oxidation-reduction gas after the voltage is applied.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device. The method includes introducing an inert gas and a material gas into a predetermined space, applying a voltage to generate plasma in the space after introducing the inert gas and the material gas so as to form a semiconductor layer on a substrate, introducing an oxidation-reduction gas in the predetermined space after the voltage is applied, and stopping the introduction of the material gas, the inert gas, and the oxidation-reduction gas after the voltage is applied.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming, on a semiconductor substrate, a sacrificial semiconductor pillar having a pillar-like shape extending in a first direction perpendicular to a main surface of the semiconductor substrate, and being formed of a first semiconductor material. The method further includes forming, around the sacrificial semiconductor pillar, a channel semiconductor layer having a tube-like shape extending in the first direction, and being formed of a second semiconductor material different from the first semiconductor material. The method further includes removing the sacrificial semiconductor pillar after the channel semiconductor layer is formed. The channel semiconductor layer is formed on electrode layers via an insulator, the electrode layers being formed on the semiconductor substrate.

Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.