Abstract: A handwritten character recognition apparatus has a character string input area of a size that allows a user to hand write a plurality of characters thereon using a stylus. A coordinate detection unit extracts a coordinate string for each stroke that forms the handwritten character string. An input completion judgement unit judges an immediately preceding handwritten character string to be complete if a time difference between a last coordinate of an immediately preceding stroke and a first coordinate of a stroke being input is at least a predetermined time, when the first coordinate of the stroke is detected in a first area of the character string input area. A character segmentation unit segments a stroke string for each character from all the strokes of the previously input hand written character string from which a character recognition unit recognizes each character and outputs a character string which is the recognition result.

Abstract: A character input apparatus accurately recognizes handwritten characters drawn one after another in a single input frame. A stroke matching unit obtains stroke information for each stroke in the inputted handwritten characters from the start/end area of the stroke in the input frame and the direction of the stroke, and detects stroke candidates for the stroke by comparing the stroke information with each set of stroke information in the stroke dictionary. An interval-based character detecting unit detects character candidates from detected stroke candidates by referring to the character dictionary that stores an stroke order for each character. With this construction, the apparatus is capable of accurately recognizing a plurality of characters drawn one after another in a single input frame.

Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate including an active region and an isolation region; an MIS transistor formed in the active region; a trench isolation structure formed in the isolation region; an insulating film covering both the MIS transistor and the trench isolation structure; and an interlevel dielectric film formed on the insulating film. An opening, which reaches part of source/drain doped regions of the MIS transistor and part of the trench isolation structure, is formed in the interlevel dielectric film. An electrode is formed to be in contact with the source/drain doped regions through the opening. The insulating film is made of a material making the insulating film function as etch stop layer for the interlevel dielectric film. A stepped portion is formed between the respective upper surfaces of the active region and the trench isolation structure. At least one of the source/drain doped regions reaches a side of the stepped portion.

Abstract: A handwritten character recognition apparatus has a character string input area of a size that allows a user to hand write a plurality of characters thereon using a stylus. A coordinate detection unit extracts a coordinate string for each stroke that forms the handwritten character string. An input completion judgement unit judges an immediately preceding handwritten character string to be complete if a time difference between a last coordinate of an immediately preceding stroke and a first coordinate of a stroke being input is at least a predetermined time, when the first coordinate of the stroke is detected in a first area of the character string input area. A character segmentation unit segments a stroke string for each character from all the strokes of the previously input hand written character string from which a character recognition unit recognizes each character and outputs a character string which is the recognition result.

Abstract: The semiconductor device of the invention includes a plurality of circuit blocks including a first circuit block and a second circuit block, a block parameter of the first circuit block being different from a block parameter of the second circuit block. In the semiconductor device, the first circuit block is formed on a first semiconductor chip, and the second circuit block is formed on a second semiconductor chip and is electrically connected with the first circuit block.

Abstract: A character extraction apparatus is provided for extracting character data for each character from a text image which is represented by first pixels corresponding to character images and second pixels corresponding to background images. The character extraction apparatus comprises a character row detecting means for detecting character rows from the text image and obtaining position data of each character row; a pixel array extracting means for extracting arrays of continuous first pixels in an area specified by the character row position data and computing position data of each of the arrays of continuous first pixels; a character array linking means for linking the arrays of continuous first pixels in the area based on the position data of the arrays of continuous first pixels; and a character extracting means for recognizing each set of arrays of continuous first pixels linked by the character array linking means as a character and outputting character data.

Abstract: The semiconductor device of the invention includes a plurality of circuit blocks including a first circuit block and a second circuit block, a block parameter of the first circuit block being different from a block parameter of the second circuit block. In the semiconductor device, the first circuit block is formed on a first semiconductor chip, and the second circuit block is formed on a second semiconductor chip and is electrically connected with the first circuit block.

Abstract: A character extraction apparatus is provided for extracting character data for each character from a text image which is represented by first pixels corresponding to character images and second pixels corresponding to background images. The character extraction apparatus comprises a character row detecting means for detecting character rows from the text image and obtaining position data of each character row; a pixel array extracting means for extracting arrays of continuous first pixels in an area specified by the character row position data and computing position data of each of the arrays of continuous first pixels; a character array linking means for linking the arrays of continuous first pixels in the area based on the position data of the arrays of continuous first pixels; and a character extracting means for recognizing each set of arrays of continuous first pixels linked by the character array linking means as a character and outputting character data.

Abstract: A character extraction apparatus is provided for extracting character data for each character from a text image which is represented by first pixels corresponding to character images and second pixels corresponding to background images. The character extraction apparatus comprises a character row detecting means for detecting character rows from the text image and obtaining position data of each character row; a pixel array extracting means for extracting arrays of continuous first pixels in an area specified by the character row position data and computing position data of each of the arrays of continuous first pixels; a character array linking means for linking the arrays of continuous first pixels in the area based on the position data of the arrays of continuous first pixels; and a character extracting means for recognizing each set of arrays of continuous first pixels linked by the character array linking means as a character and outputting character data.

Abstract: The semiconductor device of the invention includes a plurality of circuit blocks including a first circuit block and a second circuit block, a block parameter of the first circuit block being different from a block parameter of the second circuit block. In the semiconductor device, the first circuit block is formed on a first semiconductor chip, and the second circuit block is formed on a second semiconductor chip and is electrically connected with the first circuit block.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: An apparatus and a method are provided for assigning categories to words in document images. The apparatus and method extract characters and words from document images and assign categories to the words by referring to dictionaries installed in the apparatus. Furthermore, the apparatus and method correct or assign categories by referring to category correction rule dictionary.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: Provided between a control gate electrode and a channel region of the EEPROM memory cell is a capacitor. Formed on the channel region are a first gate dielectric layer of silicon oxide, a first carrier capture layer of silicon nitride, a carrier migration layer of n.sup.31 polysilicon, a second carrier capture layer of silicon nitride, and a second gate dielectric layer of silicon oxide. The carrier capture state of the carrier capture layer is changed to generate a polarization state in the capacitor, and the generated polarization state is held as data. The gate dielectric layer is not destroyed since the movement of carriers is limited to within the capacitor, and by adjusting the carrier bound energy, low-voltage drive can be accomplished.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: A non-volatile semiconductor memory cell having a novel structure is provided. The memory cell has a ring-shaped channel region formed on a semiconductor substrate, a drain region formed in a zone surrounded by the channel region, and a source region formed outside the channel region. The cell further includes a first gate insulation layer formed on the substrate in such a manner as to cover the boundary between the channel region and the drain region, a ring-shaped floating gate electrode formed on the first gate insulation layer, a second gate insulation layer formed on the floating gate electrode; and a control gate electrode which is capacitive-coupled with the floating gate via the second gate insulation layer.

Abstract: Described is a method for manufacturing semiconductor devices which includes a heat treating process for heating and cooling semiconductor substrates mounted on a boat at a predetermined pitch according to a predetermined temperature profile, in order to flatten the surface of each semiconductor substrate by reflowing an insulating film containing impurities, for example, a BPSG film formed on the substrate. In the heat treating process, one of the control factors which affects the formation of grains or particles due to the impurities contained in the insulating film is set so as to prevent the impurities from generating grains or particles during the heat treatment. Also disclosed is a method of preventing the generation of grains or particles by widening the pitch of the mounted substrates.

Abstract: A semiconductor laser in which an InGaAsP active layer serving as light emitting layer and formed in the shape of a stripe on the surface of a flat InP first clad layer, and an InP second clad layer that is wider than the InGaAsP active layer and formed on the InGaAsP active layer are buried in an InP burying layer. The stripe direction is the <011> direction, an etched mirror is formed in the vicinity of the end of the active layer, and an opto-electronic integrated circuit is formed by integrating the electric device and photo detecting device on the same substrate. The substrate is a semi-insulating substrate, and the electric device and photo detecting device are formed on the InGaAsp or InGaAs layer formed on the InP burying layer by crystal growth.

Abstract: Disclosed is a method for burying a step in a semiconductor substrate in which (1) SiO.sub.2 layer is formed on a lower part of the step, (2) photoresist layer with equal thickness to the height of the step on the SiO.sub.2 layer at a portion corresponding to the lower part of the step, (3) sputter-SiO.sub.2 layer is formed by sputtering on the photoresist layer and SiO.sub.2 layer, (4) another photoresist layer is formed on the sputter-SiO.sub.2 layer, (5) the another photoresist layer and sputter-SiO.sub.2 layer are removed, and (6) the SiO.sub.2 layer and photoresist layer are removed. By this method, semiconductor substrate with flatness of within 50 nm in a 6-inch wafer can be obtained.