Patents by Inventor Ichiro Nakatsukasa

Ichiro Nakatsukasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4811073
    Abstract: A gate array arrangement formed on a semiconductor chip includes a plurality of I/O cells aligned along the four sides of the chip and a plurality of basic cells aligned in a plurality of rows extending parallelly to each other. A ground bus line and a power bus line extend in a space between the I/O cells and basic cells. The lines from the I/O cells are connected to the bus lines, and lines from basic cells are connected to bus lines. In this manner, the power supply lines between the I/O cells and basic cells are connected indirectly through the bus line, thereby allowing the determination of pitch of the I/O cells and pitch of basic cells independently of each other.
    Type: Grant
    Filed: April 18, 1988
    Date of Patent: March 7, 1989
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yuji Kitamura, Ichiro Nakatsukasa