Abstract: A semiconductor integrated circuit with a short turn-off time in which a high breakdown voltage semiconductor element and a Schottky barrier diode are fabricated into a semiconductor substrate, is disclosed. In the integrated circuit, within a semiconductor substrate of a first conductivity type, a diffusion layer with a low impurity concentration disposed deeply which is used as one layer of a high breakdown voltage semiconductor element formed by a high breakdown voltage process and a diffusion layer with a high impurity concentration disposed more shallowly than the diffusion layer with a low impurity concentration, are formed so as to partially couple with each other. The diffusion layer with the high impurity concentration is used for both the ohmic contact for the electrode of the diffusion layer with the low impurity concentration and for a guard ring for a Schottky barrier diode.

Abstract: A PNPN switch has a transistor for protecting the switch from the dv/dt effect, which is so connected as to shortcircuit one outermost PN junction PN of the switch. The transistor is driven by a drive circuit and not through the outer outermost PN junction of the switch by a drive circuit. The drive circuit is so designed that, in a transient mode, it operates as a transistor element and a capacitive element and, in a DC mode, it operates solely as a capacitive element. To this end, a transistor is used as the drive circuit. A level shift element is connected in series with the emitter-base junction of the drive transistor. The series circuit of the level shift element and the emitter-base junction is connected across the other PN junction and the collector of the drive transistor is connected to the base of the dv/dt protective transistor.

Abstract: A memory circuit comprising a memory cell for storing information, constituted of semiconductor circuit elements and the associated circuit elements, and a control input section provided on the input side of the memory cell for controlling the memory cell, constituted of transistor means and current control means, wherein one of ON and OFF states is selected and also held in accordance with more than two logic input signals supplied to the control input section and no power is consumed to hold the OFF state.

Abstract: A trigger circuit for a thyristor comprising at least one of each of an NPN transistor and a PNP transistor and a PNPN switch to trigger a 4-terminal thyristor by feeding a collector current of the PNP transistor into a cathode gate of the thyristor and by taking out a collector current of the NPN transistor from an anode gate of the thyristor. An emitter of the PNP transistor is connected to a power supply through a resistor, and a cathode and an anode of the PNPN switch is connected to a base of the PNP transistor and a base of the NPN transistor, respectively. By controlling the on-off operation of the PNPN switch, the thyristor is selectively triggered, so that the trigger circuit can be operated by a single low voltage supply and does not require any separate circuit for holding a conducting state of the thyristor.

Abstract: In a semiconductor switch circuit employing at least one 4-terminal PNPN switch having a cathode gate and an anode gate for switching an AC signal, a current supplying circuit is connected to the cathode gate of the PNPN switch, and a current sinking circuit of constant-current type is connected to the current supplying circuit and the anode gate of the PNPN switch through a current change-over circuit. Depending on the potential of the PNPN switch, the current change-over circuit supplies selectively the current flowing into the current supplying circuit and the current flowing out from the anode gate of the PNPN switch to the current sinking circuit.The current supplying circuit operates as a constant-current circuit owing to the current sinking function of the current sinking circuit. The semiconductor switch circuit is simple in circuit construction and can be economically integrated into an integrated circuit form.

Abstract: A semiconductor switch has a pair of PNPN switches connected in an inverse-parallel mode and each includes a switching circuit for protection against the rate effect. Each switch has its gate terminal multi-connected through a capacitive element to provide a terminal, which is connected to the output terminal of a control circuit for generating a voltage pulse in a repetitive manner to bear the difference of potential between the PNPN switches and a capacitive element by means of the capacitive element and to drive the PNPN switches with the aid of a variation of voltage produced in the control circuit.

Abstract: A semiconductor switch circuit comprises a PNPN switch with a PNPN semiconductor four-layered structure equivalently including first and second transistors and a gate terminal, a load current dividing circuit including at least one transistor, a variable impedance bypass circuit including at least one transistor, and a capacitive element. The base and the collector of the transistor included in the load current dividing circuit are connected to the cathode and the anode of the PNPN switch, respectively. The collector and the emitter of the transistor included in the variable impedance bypass circuit are connected to the P-type base of the second transistor of the PNPN switch and to the emitter of the transistor of the load-current-dividing circuit, respectively. The base of the transistor of the variable impedance bypass circuit is connected to the anode of the PNPN switch through the capacitive element and is controlled for gate turn-off operation.

Abstract: A semiconductor switch circuit comprises a PNPN switch with a gate terminal and having an equivalently four-layered PNPN structure, and a load-current-dividing circuit including at least a transistor. The base and the collector of the transistor included in the load-current-dividing circuit are connected to the cathode and the anode of the PNPN switch, respectively. The load current is divided into two parts of the current. One part of the load current flows into the base of the transistor through the anode and the cathode of the PNPN switch, while the remaining part of the load current flows into the collector of the transistor. Since the greater part of the load current flows into the collector of the transistor, the PNPN switch is not burdened with a large current. Thus, the semiconductor switch circuit permits the gate turn-off operation of the PNPN switch with a self-holding ability, thereby making it possible to cut off a large current.

Abstract: A constant current circuit includes two characteristic-correlated PNP transistors connected to a constant voltage source and having common-connected emitters and common-connected bases and an NPN transistor. A constant current is taken out of a collector of a first PNP transistor. A collector of a second PNP transistor is connected to a base of the NPN transistor and the common-connected emitters of the first and second PNP transistors is connected to a collector of the NPN transistor to form a negative feedback circuit in the first PNP transistor, whereby when a current gain of the second PNP transistor which is characteristic corelated to the first PNP transistor is high a large amount of feedback is applied and when the current gain is low a small amount of feedback is applied so that the magnitude of the output constant current taken from the collector of the first PNP transistor is adjusted.

Abstract: A stable semiconductor switch comprising a PNPN switch, a transistor, a driving device, and diodes. The PNPN switch is composed of four-layered PNPN structure and has three PN-junctions, an anode, an anode gate, a cathode gate, and a cathode. The collector and the emitter of the transistor are connected to the cathode gate and the cathode of the PNPN switch, respectively. The driving device has its one end connected to the anode gate of the PNPN switch and its other end connected to the base of the transistor so as to drive the transistor in transient state. The diodes are connected between the driving device and the emitter of the transistor in a manner so that, when the PNPN switch is controlled to fire and a back current tends to flow through the PNPN switch temporarily, the back current does not flow through the transistor so as to prevent the transistor from causing any abnormal actions such as oscillation.

Abstract: A light-emitting diode element comprises a semiconductor wafer including a pair of a p-type semiconductor region and an n-type semiconductor region forming a pn junction, an inclined first electrode provided on at least one of the peripheral edges of the surface of one of the semiconductor regions in the semiconductor wafer, and a flat second electrode provided on the surface of the other semiconductor region. A light-emitting diode device is provided in which a plurality of such light-emitting diode elements are respectively received in a plurality of openings of a substrate having a first wiring conductor group and a second wiring conductor group electrically connected to the first and second electrodes respectively of the light-emitting diode elements by a low-melting metal. Thus, these light-emitting diode elements can be mounted on the single substrate in a high package density, and the light-emitting diode device of simple construction can be easily assembled.

Abstract: A semiconductor switch of a PNPN structure comprises a PNPN switch of an equivalently four-layered structure including a P-type anode, N-type cathode, N-type gate and P-type gate, a first NPN transistor, a second PNP transistor, a level shifting circuit, and an impedance element, wherein the impedance element is connected between the collector and emitter of the first transistor, the first transistor has its collector and emitter connected to the P-type gate and N-type cathode respectively, and the second transistor has its emitter and base connected to the P-type anode and N-type gate, respectively, and has its collector connected to the base of the first transistor through the level shifting circuit.

Abstract: A memory circuit is comprised of a memory cell of PNPN- equivalent 4-layer construction, a selective input circuit composed of a pair of an NPN transistor and a PNP transistor, and a read-out circuit for reading the information stored in the memory cell. The emitters of the transistors included in the selective input circuit are connected to one of the selective input terminals, the bases thereof to the other selective input terminal, the collector of one of the transistors to the write input terminal of the memory cell, and the collector of the other transistor to the input terminal of the read-out circuit. Thus, both the writing and reading operations are controlled from the same selective input terminal, and power consumption of the selective input circuit in the holding mode is substantially zero.

Abstract: A semiconductor switch is composed of at least a 4-terminal PNPN switch. The cathode gate and the anode gate of the PNPN switch are connected to a current-supplying type constant-current circuit with a power supply for feeding a current into the cathode gate and to a current-sinking type constant-current circuit without any power supply for taking out a current from the anode gate, respectively. A change-over circuit is connected between both the constant-current circits for automatically selecting a path of a drive current from the current-supplying type constant-current circuit to either selected one of the cathode gate and the anode gate or the current-sinking type constant-current circuit in response to the electrical potential of the PNPN switch. The semiconductor switch circuit composed of the 4-terminal PNPN switch may be thus controlled economically with a single power supply without any wasteful power consumption.

Abstract: A semiconductor switch device comprising a PNPN switch having an equivalent four-layer structure, a transistor, two impedance elements and a capacitive element, wherein the transistor and one of the impedance elements are connected in parallel with each other, the parallel circuit thus formed is connected between the P base and the N cathode of the PNPN switch, the capacitive element is connected between the base of the transistor and a terminal maintained at a constant potential, and the other impedance element is connected between the base and the emitter of the transistor, whereby the semiconductor switch has a high tolerance to dv/dt and can be closed with high sensitivity.

Abstract: A semiconductor switch comprising a PNPN switch having an equivalently four-layer structure of p, n, p and n regions and three PN junctions; a transistor; two impedance elements and a capacitive element, wherein the transistor and one of the impedance elements is connected in parallel to each other, the parallel circuit thus formed being connected between the p base and the cathode of the PNPN switch, the capacitive element is connected between the base of the transistor and the anode of the PNPN switch, and the other impedance element is connected between the base and the emitter of the transistor, so that the obtained semiconductor switch has a high dv/dt withstandingness independent of the potential at the anode or cathode and a high breakdown voltage, can be closed with a small control current and is adapted for high speed switching.

Abstract: A light activated semiconductor switch device comprising a light activated PNPN switch, an impedance element, a switching element, and a capacitance element. The impedance element and switching element are connected in parallel across the cathode gate and the cathode or across the anode and the anode gate of the light activated PNPN switch, and the switching element is turned on by the current supplied through the capacitance element, so that the device can operate with improved tolerance to dv/dt and high turn-on sensitivity.

Abstract: A semiconductor bidirectional switch circuit comprises a bidirectional switch including two thyristors connected in antiparallel relationship. A bypass circuit is connected to each of the two thyristors for bypassing a part of a main current flowing through the thyristor from the anode to the cathode of the thyristor.

Abstract: A memory circuit comprises a semiconductor element circuit having equivalently a PNPN four-layer structure, at least an NPN transistor and a diode. An N-type emitter of the semiconductor element circuit is connected to the base of the NPN transistor, while a P-type base of the circuit is connected to the collector of the NPN transistor through the diode. The semiconductor element circuit has a positive feedback loop which is additionally provided with another feedback loop extending across the P-type base and the N-type emitter of the semiconductor element circuit, whereby in the ON holding state of the memory circuit the semiconductor element circuit is operated as a current stabilizing circuit and the transistor included in the additional feedback loop is stabilized in a controlled staturation state. The memory circuit can thus be operated at a high speed with a low power consumption.

Abstract: A memory circuit for providing a zero OFF-holding power under the logical control of three inputs comprises a memory cell including a semiconductor element circuit of equivalently four PNPN layer structure and a logical input section including at least one PNP transistor and NPN transistor with the collector of the PNP transistor connected to the base of the NPN transistor. The NPN transistor in the logical input section has its collector connected to the control gate of the memory cell, and logical input signals are applied to the emitter and base of the PNP transistor and the emitter of the NPN transistor in the logical input section, respectively.