Abstract: A printed circuit layout system using two or more of the following sub-systems: a pattern processing subsystem, a pattern design rule check subsystem, and a pattern connectivity verification characterizes any circuit pattern by a set of rectangles, each rectangle identified by a potential number and a layer, number and coordinates, and identifies terminals by potential number, layer number, and terminal names. The system eliminates the need to perform pattern OR processing and electrical connectivity search, as required by conventional schemes. The reforming and checking processes for the layout patterns are executed by a simple high speed method, making use of the features of the layout data. The system includes efficient methods for notch elimination, design rule checking, and connectivity checking.