Abstract: A circuit includes: a first line (11) in which one end thereof (11a) is coupled to a first signal input terminal (la); a second line (12) in which one end thereof (12a) is grounded and the other end thereof (12b) is coupled to a first signal output terminal (4a), the second line (12) being electromagnetically coupled to the first line (11); a third line (13) in which one end thereof (13a) is open, the third line (13) being electromagnetically coupled to the second line (12); a fourth line (21) in which one end thereof (21a) is coupled to the other end (11b) of the first line (11) and the other end thereof (21b) is open; a fifth line (22) in which one end thereof (22a) is coupled to a second signal output terminal (4b) and the other end thereof (22b) is grounded, the fifth line (22) being electromagnetically coupled to the fourth line (21); and a sixth line (23) in which one end thereof (23a) is coupled to the other end (13b) of the third line (13) and the other end thereof (23b) is coupled to a second signal

Abstract: A first balanced/unbalanced circuit is provided that splits a first mixed wave outputted from an even harmonic mixer into first and second split signals, outputs the first split signal that is in phase with the first mixed wave to a first output terminal, and outputs the second split signal that is opposite in phase to the first mixed wave to a second output terminal. Further, a second balanced/unbalanced circuit is provided that splits a second mixed wave outputted from the even harmonic mixer into third and fourth split signals, outputs the third split signal that is in phase with the second mixed wave to the second output terminal, and outputs the fourth split signal that is opposite in phase to the second mixed wave to the first output terminal.

Abstract: Provided is an amplifier with a test oscillator for a high frequency characteristic monitor, which has small power loss in a normal operation state and secures good noise performance while it is possible to equip both a transmitter IC and a receiver IC with the amplifier. In a high frequency IC including an amplifier including an inductive load and a test oscillator arranged in a same chip, the test oscillator commonly uses the inductive load of the amplifier, the amplifier has a bias voltage terminal to switch an operation state into an active state/inactive state, and the oscillator has a bias voltage terminal to switch an operation state into an active state/inactive state. In a test operation mode, the amplifier is inactivated and the test oscillator is activated and in a normal operation mode, the amplifier is activated and the test oscillator is inactivated.

Abstract: A bias circuit includes a first p-n junction element supplied with a current by a first current source connected to a low-voltage side of the first p-n junction element and a base terminal of a second transistor, a second p-n junction element supplied with a current by a second current source, the second current source connected to a low-voltage side of the second p-n junction element and a base terminal of a first transistor, the first and second transistors connected at their emitter terminals to a third current source and receiving base voltages generated by the first and second p-n junction elements, respectively. The second transistor and the first transistor constitute a differential pair in which, at a collector terminal of the second transistor, a current having a temperature coefficient that is substantially twice the temperature coefficient of the current of the second current source is obtained.

Abstract: Provided is an amplifier with a test oscillator for a high frequency characteristic monitor, which has small power loss in a normal operation state and secures good noise performance while it is possible to equip both a transmitter IC and a receiver IC with the amplifier. In a high frequency IC including an amplifier including an inductive load and a test oscillator arranged in a same chip, the test oscillator commonly uses the inductive load of the amplifier, the amplifier has a bias voltage terminal to switch an operation state into an active state/inactive state, and the oscillator has a bias voltage terminal to switch an operation state into an active state/inactive state. In a test operation mode, the amplifier is inactivated and the test oscillator is activated and in a normal operation mode, the amplifier is activated and the test oscillator is inactivated.

Abstract: A bias circuit includes a first p-n junction element supplied with a current by a first current source connected to a low-voltage side of the first p-n junction element and a base terminal of a second transistor, a second p-n junction element supplied with a current by a second current source, the second current source connected to a low-voltage side of the second p-n junction element and a base terminal of a first transistor, the first and second transistors connected at their emitter terminals to a third current source and receiving base voltages generated by the first and second p-n junction elements, respectively. The second transistor and the first transistor constitute a differential pair in which, at a collector terminal of the second transistor, a current having a temperature coefficient that is substantially twice the temperature coefficient of the current of the second current source is obtained.

Abstract: The present invention provides a disk storage system with a low error rate, which is suitable for reduction in size. The other end of the signal line, which is connected with a read head at one end, is connected with a head bias circuit to apply a sense current to the read head and a pair of first and second capacitance elements for allowing the read signal element formed by the read head to pass, a loop is provided for amplifying the read signal obtained through the first and second capacitance elements by supplying the read signal to an input terminal of a differential amplifying circuit and for converting the amplified signal into the current by transconductance and providing a positive feedback of the amplified signal to the input terminal of the differential amplifying circuit.

Abstract: The present invention provides a disk storage system with a low error rate, which is suitable for reduction in size. The other end of the signal line, which is connected with a read head at one end, is connected with a head bias circuit to apply a sense current to the read head and a pair of first and second capacitance elements for allowing the read signal element formed by the read head to pass, a loop is provided for amplifying the read signal obtained through the first and second capacitance elements by supplying the read signal to an input terminal of a differential amplifying circuit and for converting the amplified signal into the current by transconductance and providing a positive feedback of the amplified signal to the input terminal of the differential amplifying circuit.