Abstract: A motion picture coding apparatus for storage medium of a video rate is produced at a low cost. The coding apparatus includes an input picture re-arranging unit for changing the order of frames of input motion pictures, a storage circuit for storing therein decoded pictures of intra-coded and predictive coded pictures, an address generating unit, a motion detector for performing multi-stage motion vector search, a predictive signal generating unit for outputting an inter-frame predictive signal and a predictive difference signal, a quantizing unit, a variable length coding unit, and locally decoding unit. The predictive signal generating unit simultaneously fetches data read out from the storage circuit to the motion detector for final stage vector search to reduce access to the storage circuit.

Abstract: A processor array has first through N-th processor. Each of first through (N-1)-th switching devices is connected between preceding and succeeding consecutively numbered ones of the first through the N-th processors. Each processor has at least one processor module coupled between a processor input bus and a processor output bus. A controlling unit controls the switching devices so that the input and output buses of the processor are selectively connected together. Each processor includes a feedback bus which is connected to the module. The (N-1)-th switching devices are controlled so that the feedback buses of the processor are selectively connected in series in compliance with the manner in which the processor input and output buses of the processors are connected together. The controlling unit may also control the processor modules of each processor.

Abstract: This is a real time video signal processor for real time digital processing of video signals with a plurality of unit processors. All the unit processors are connected in parallel between an input bus and an output bus. Each unit processor consists of an input section connected to the input bus, a processing section for digital processing of video signals written into the input section, and an output section for supplying video signals processed by the processing section to the output bus. There is provided control sections for generating control signals to command what picture block of each frame is to be written into each unit processor and what picture block of each processed frame is to be outputted. Generally, each unit processor takes in a greater picture block than the picture block to be processed, and each processor independently accomplishes digital processing of the picture block assigned to it without communicating with any other unit processor.

Abstract: In a real-time video signal processor for processing an input digital video signal divisible into a succession of principal blocks each of which has at least one scanning line and a time duration shorter than a frame period, each principal block is divided into at least two partial blocks with each scanning line divided into the respective partial blocks. A plurality of signal processing modules are assigned with the respective partial blocks of each principal block, respectively. Responsive to the input digital video signal and an additional digital video signal, the signal processing modules process the respective partial blocks of each principal block into processed signals during the time duration, respectively. Each processed signal comprises a first partial signal used as an output signal of the processor and a second partial signal.