Abstract: A semiconductor storage device having a security function for imposing limitation on data rewriting includes: at least one non-volatile memory cell array block which is capable of receiving concurrent electrical erasure; at least one memory region, each one of said at least one memory region being provided in the at least one memory cell array block, for storing a security release key; at least one non-volatile storage means for storing a security registration lock corresponding to each of the at least one memory cell array block; a determination circuit for generating a security release signal using the security release key and the security registration lock; and a memory cell array data output switching circuit for outputting security released data externally.

Abstract: A nonvolatile semiconductor memory device of the present invention includes: a main memory circuit including memory cells arranged in a matrix form, the memory cells being formed of electrically writable and erasable floating gate transistors each provided at an intersection of a bit line and a word line; and a redundant substitution information memory circuit including a plurality of memory cells formed of the electrically writable and erasable floating gate transistors, wherein one end of each memory cell formed of the floating gate transistors in the redundant substitution information memory circuit can be electrically connected to and disconnected from the bit line in the main memory circuit by a selection transistor so as to supply the memory cells in the redundant substitution information memory circuit with current for writing and reading operations via the bit lines.

Abstract: A nonvolatile semiconductor memory device of the present invention includes: a main memory circuit including memory cells arranged in a matrix form, the memory cells being formed of electrically writable and erasable floating gate transistors each provided at an intersection of a bit line and a word line; and a redundant substitution information memory circuit including a plurality of memory cells formed of the electrically writable and erasable floating gate transistors, wherein one end of each memory cell formed of the floating gate transistors in the redundant substitution information memory circuit can be electrically connected to and disconnected from the bit line in the main memory circuit by a selection transistor so as to supply the memory cells in the redundant substitution information memory circuit with current for writing and reading operations via the bit lines.

Abstract: A coincidence circuit outputs a coincidence signal when a specific address derived from a specific address setting circuit and an input address coincided with each other. A counter circuit outputs a pulse signal each time the coincidence signal is inputted to a specified number of times. According to the pulse signal, a multiplexer switching circuit toggles the output of the multiplexer to the false data side connecting to a false data conversion circuit over a specified range of addresses. Thus, when addresses of the memory cell array are scanned in an unauthorized user's attempt at an illegal read, the false data is mixed into the read data at a specified period, making it difficult to reproduce correct data or correct programs from the acquired data. Consequently, with this memory device, it is impossible to reproduce correct data or correct programs even if an attempt to illegally read memory contents is made.

Abstract: A semiconductor storage device having a security function for imposing limitation on data rewriting includes: at least one non-volatile memory cell array block which is capable of receiving concurrent electrical erasure; at least one memory region, each of which is provided in the at least one memory cell array block, for storing a security release key; at least one non-volatile storage means for storing a security registration lock corresponding to each of the at least one memory cell array block; a determination circuit for comparing a value which is generated based on the security release key against a value which is generated based on the security registration lock to determine whether or not to grant release of the security function; and a memory cell array data output switching circuit for, when an output signal from the determination circuit indicates a matching result of comparison between the value which is generated based on the security release key and the value which is generated based on the secu