Abstract: An image forming apparatus comprises a data quantity determining section (4-1) for determining a data quantity of image information based on the received image attribute information; a memory section area determining section (4-2) for determining a necessary memory section area necessary for processing raster data for the image data based on a determination result of the data quantity determining section; and a memory state setting section (4-3) for setting the memory sections (3-1, 3-2, 3-3) at either active or inactive state based on a determination result of the memory section area determining section (4-2).

Abstract: A printer includes a plurality of cassettes and a cassette is selected from the cassettes. The printer comprises a print information memory, paper information memory, cassette information memory, cassette selector, and data editor. The print information memory stores print information contained in print data therein. The print information includes a size of the print paper and an orientation of the print paper with respect to a direction of travel of the print paper. If a size of print paper specified by the print information is different from a size of print paper accommodated in a paper cassette selected last time, a first paper cassette is selected which accommodates print paper of a size specified by the print information. If the print information specifies print paper of a same size as the print paper accommodated in a paper cassette selected last time, a second paper cassette is selected which accommodates print paper oriented in a way different from the cassette selected last time.

Abstract: An output buffer circuit drives an output terminal of an integrated circuit by means of at least two buffer circuits. A buffer control circuit in the output buffer circuit selectively enables or disables the buffer circuits to provide a driving capability suitable for the load connected to the output terminal. The buffer control circuit can decide which buffer circuits to disable by sensing the transition time of a signal output from the output terminal following a reset.

Abstract: A memory system includes a plurality of output buffers each of which outputs one of a plurality of one-bit signals forming data. The output buffers are put into a plurality of buffer groups. The memory system further includes a controller for feeding timing signals to the corresponding buffer groups via delay circuits having mutually different time constants, respectively. The timing signals include certain timing which causes the output buffers to output the corresponding one-bit signals. Since the foregoing certain timing is delayed depending on the time constants of the delay circuits, although the output buffers in the same buffer group output the corresponding one-bit signals simultaneously, the output buffers in the different buffer groups output the corresponding one-bit signals with mutually different timing.