Patents by Inventor Ichiro Yamamoto

Ichiro Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040155265
    Abstract: In a semiconductor device including at least one p-channel type MOS transistor, a silicon dioxide layer is formed on a silicon substrate, and a gate electrode is formed on the silicon dioxide layer. The gate electrode silicon has a three-layered structure including a silicon-seed layer formed on the silicon dioxide layer, a silicon/germanium layer formed on the silicon-seed layer, and a polycrystalline silicon layer on the silicon/germanium layer. An average grain size of polycrystalline silicon in the polycrystalline silicon layer is at most 100 nm, and p-type impurities are substantially uniformly distributed in the gate electrode along a height thereof, and the germanium atoms are diffused from the silicon/germanium layer into the silicon-seed layer at high density.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 12, 2004
    Inventors: Ichiro Yamamoto, Naohiko Kimizuka
  • Publication number: 20040135217
    Abstract: A semiconductor device is provided which is capable of improving its reliability by using a material having a high relative dielectric constant as a material for its gate insulating film, by suppressing degradation of an EOT (Equivalent oxide Thickness) and by preventing crystallization of the material having a high relative dielectric constant. The semiconductor device (Field Effect Transistor) has a silicon substrate, a seed layer made up of silicon oxide, a gate insulating film made of amorphous hafnium aliminate and a gate electrode made up of polycrystalline silicon formed the gate insulating film. The gate insulating film is so formed that a hafnium concentration decreases monotonously or step by step, whereas an aluminum concentration increases monotonously or step by step along a direction of a thickness of the gate insulating film from the silicon substrate side toward the gate electrode.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 15, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Ichiro Yamamoto
  • Publication number: 20040135186
    Abstract: A semiconductor device is provided which has a capacitor insulating film made up of zirconium aliminate being an amorphous film obtained by having crystalline dielectric contain amorphous aluminum oxide and having its composition of AlXZr(1−X)OY, (0.05≦x≦0.3), hereby being capable of preventing, in a process of forming a capacitor of MIM (Metal Insulator Metal) structure, dielectric breakdown of a capacitor insulating film while a relative dielectric constant of a metal oxide film used as the capacitor insulating film is kept high.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 15, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Ichiro Yamamoto
  • Patent number: 6710407
    Abstract: A p-channel type field effect transistor incorporated in a semiconductor device has a gate electrode on a gate insulating layer, and the gate electrode is constituted by an amorphous silicon layer on the gate insulating layer, a silicon-germanium layer on the amorphous silicon layer, a polysilicon layer on the silicon germanium layer, a barrier layer of silicon oxide on the polysilicon layer residue of a cap silicon layer on the barrier layer and a cobalt silicide layer on the residue; while heat is being applied, boron, which has been ion implanted into the polysilicon layer and active region on both sides of the gate electrode, is activated with the assistance of germanium, and the barrier layer blocks the boundary between the cap silicon layer and the cobalt layer from the germanium so that the cobalt silicide forms a continuous layer without any coagulation.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: March 23, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Ichiro Yamamoto
  • Patent number: 6710060
    Abstract: The present invention relates to a compound represented by the following formula (I) or a salt thereof, or a pharmaceutical composition containing the compound as an effective ingredient: (wherein A represents, for example, phenyl group substituted with R1 and R2 or unsubstituted thienyl group; R1 and R2 each independently represent, for example, hydrogen atom, halogen atom or lower alkoxycarbonyl group; R3 represents, for example, hydrogen atom; R4 represents, for example, lower alkyl group; R5 represents, for example, lower alkoxy group; R6 represents, for example, hydrogen atom; R7 and R8 each represent, for example, hydrogen atom, respectively; X represents, for example, a single bond; Y represents, for example, methylene group or benzylidene group substituted with R1; and Z represents, for example, methylene group.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: March 23, 2004
    Assignee: Mochida Pharmaceutical Co., Ltd.
    Inventors: Ichiro Yamamoto, Manabu Itoh, Fumiaki Yamasaki, Yutaka Miyazaki, Shinichi Ogawa
  • Patent number: 6696719
    Abstract: A semiconductor device in which a cell capacitor with an MIM or MIS structure is formed using a conductive material with a low resistivity for the upper electrode and a resistance element is formed using a conductive material with high resistance without increasing the complexity of the fabrication process. A plate electrode used for the upper electrode of the cell capacitor and for the resistance element is made by forming a three-layer structure including a low resistance conductive material layer, an insulating film layer on the low resistance conductive material layer, and a high resistance conductive material layer on the insulating film layer, patterning the three-layer structure in the same shape, and using the low resistance conductive material layer as the upper electrode of the cell capacitor and the high resistance conductive material layer as the resistance element.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: February 24, 2004
    Assignee: NEC Corporation
    Inventor: Ichiro Yamamoto
  • Patent number: 6674704
    Abstract: An apparatus for manufacturing a disc drive comprises an adjusting element, put in contact with a disc table engaged with a rotational shaft of a drive motor via an engaging portion, for varying an inclination of the disc table which is swingable with a point of support at the engaging portion, a non-contact displacement measuring unit for detecting, the inclination of the disc table varied by the adjusting element, control unit for receiving a detection signal from the non-contact displacement measuring unit and stopping rotation of the drive motor when the inclination of the disc table has decreased to a predetermined value or less, and an adhesive supply unit for fixing the disc table to the rotational shaft of the drive motor which has been stopped by the control unit.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: January 6, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Yamamoto, Motoji Oono
  • Patent number: 6642257
    Abstract: The present invention relates to a compound represented by Formula (I) below: (wherein A represents, for example, phenyl group substituted by R1 and R2, or an unsubstituted furyl group or an unsubstitued thienyl group; R1 represents, for example, hydrogen atom, fluorine atom, chlorine atom, trifluoromethyl group, nitro group, cyano group or methyl group while R2 represents, for example, hydrogen atom; R3 represents, for example, hydrogen atom or methyl group; R4 represents, for example, hydrogen atom or methyl group; R5 represents ethoxy group or isopropoxy group; X represents group: —CH(OH)— or methylene group; and Z represents, for example, a single bond or methylene group unsubstituted or substituted by hydroxyl group), and its salts, and medicinal compositions containing, as their active ingredient, the above compound or its salts.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: November 4, 2003
    Assignee: Mochida Pharmaceutical Co., Ltd.
    Inventors: Ichiro Yamamoto, Manabu Itoh, Fumiaki Yamasaki, Yasushige Akada, Yutaka Miyazaki, Shinichi Ogawa
  • Patent number: 6630393
    Abstract: A method for manufacturing a high dielectric constant insulating film made of a metal oxide on a silicon substrate is provided using a material gas mixture containing an oxidizing agent without forming silicon oxide layer on a silicon substrate. The manufacturing method includes the steps of placing the semiconductor substrate into a reaction chamber; introducing an organic metal material, oxidizing agent, and a material having a reducing action; and forming a high dielectric constant gate insulating film on the semiconductor substrate by a chemical reaction in the reaction chamber.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: October 7, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Ichiro Yamamoto
  • Publication number: 20030173895
    Abstract: An organic light emitting diode color display unit has a substrate, an organic electroluminescent device formed on the substrate, a transparent cover plate disposed opposite to the substrate and a color filter element formed on the transparent cover plate. The organic electroluminescent device includes an electroluminescent zone comprising a thin film of an organic electroluminescent material. The color filter element is spaced from the organic electroluminescent device and associated with the organic electroluminescent device. Light from the organic electroluminescent device is emitted from the transparent cover plate.
    Type: Application
    Filed: January 30, 2003
    Publication date: September 18, 2003
    Inventors: Yoshifumi Kato, Kazuyoshi Takeuchi, Ichiro Yamamoto
  • Patent number: 6602722
    Abstract: A barium strontium titanate is the ferroelectric substance with the perovskite structure available for a capacitor as a dielectric layer, and is crystallized through a high temperature heat treatment, in which the barium strontium titanate is further subjected to a low temperature heat treatment under the crystallizing temperature of the barium strontium titanate for eliminating impurities such as carbon and hydrogen therefrom so that the leakage current is drastically reduced.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: August 5, 2003
    Assignee: NEC Corporation
    Inventors: Ichiro Yamamoto, Toshihiro Iizuka, Yoshitake Kato
  • Patent number: 6534815
    Abstract: A semiconductor memory device includes an interlayer insulating film, a contact film, a crystallization preventing film and a conductive film. The interlayer insulating film is formed on a semiconductor substrate to cover a source/drain region of a MOS transistor. The source/drain region is formed in the semiconductor substrate. The contact film with a first impurity ion concentration contacts the source/drain region. The contact film is formed to partially embed a contact hole along side wall of the contact hole formed to pass through the interlayer insulating film to the source/drain region. The crystallization preventing film with a second impurity ion concentration is formed on the contact film to completely embed the contact hole. The first impurity ion concentration is higher than the second impurity ion concentration. The conductive film with a third impurity ion concentration is formed on a surface of the crystallization preventing film above the interlayer insulating film to have an uneven portion.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: March 18, 2003
    Assignee: NEC Corporation
    Inventor: Ichiro Yamamoto
  • Publication number: 20030049919
    Abstract: A p-channel type field effect transistor incorporated in a semiconductor device has a gate electrode on a gate insulating layer, and the gate electrode is constituted by an amorphous silicon layer on the gate insulating layer, a silicon germanium layer on the amorphous silicon layer, a polysilicon layer on the silicon germanium layer, a barrier layer of silicon oxide on the polysilicon layer residue of a cap silicon layer on the barrier layer and a cobalt silicide layer on the residue; while heat is being applied, boron, which has been ion implanted into the polysilicon layer and active region on both sides of the gate electrode, is activated with the assistance of germanium, and the barrier layer blocks the boundary between the cap silicon layer and the cobalt layer from the germanium so that the cobalt silicide forms a continuous layer without any coagulation.
    Type: Application
    Filed: August 28, 2002
    Publication date: March 13, 2003
    Applicant: NEC CORPORATION
    Inventor: Ichiro Yamamoto
  • Publication number: 20020188006
    Abstract: The present invention relates to a compound represented by the following formula (I) or a salt thereof, or a pharmaceutical composition containing the compound as an effective ingredient: 1
    Type: Application
    Filed: October 4, 2001
    Publication date: December 12, 2002
    Applicant: Mochida Pharmaceutical Co., Ltd.
    Inventors: Ichiro Yamamoto, Manabu Itoh, Fumiaki Yamasaki, Yutaka Miyazaki, Shinichi Ogawa
  • Publication number: 20020153579
    Abstract: A semiconductor device with a thin film having a high dielectric constant and uniform film thickness. The semiconductor device comprises, in an embodiment, an electrode which is made of a metal or a metal nitride and which is formed on a silicon layer via a dielectric film. The dielectric film has a multi-layer structure comprising an amorphous oxide film on the side of the silicon layer and a metal oxide film on the side of the electrode. In another embodiment, the semiconductor device comprises an electrode which is made of silicon (Si) or a silicon germanium (SiGe) and which is formed on a silicon layer via a dielectric film. In such case, the dielectric film has a multi-layer structure comprising a first amorphous oxide film on the side of the silicon layer, a second amorphous oxide film on the side of the electrode, and a metal oxide film between the first and second amorphous oxide films.
    Type: Application
    Filed: April 19, 2002
    Publication date: October 24, 2002
    Applicant: NEC CORPORATION
    Inventor: Ichiro Yamamoto
  • Publication number: 20020119617
    Abstract: A barium strontium titanate is the ferroelectric substance with the perovskite structure available for a capacitor as a dielectric layer, and is crystallized through a high temperature heat treatment, in which the barium strontium titanate is further subjected to a low temperature heat treatment under the crystallizing temperature of the barium strontium titanate for eliminating impurities such as carbon and hydrogen therefrom so that the leakage current is drastically reduced.
    Type: Application
    Filed: April 30, 2002
    Publication date: August 29, 2002
    Applicant: NEC Corporation
    Inventors: Ichiro Yamamoto, Toshihiro Iizuka, Yoshitake Kato
  • Patent number: 6413833
    Abstract: A method for forming hemispherical grains (HSG) on a cylindrical bottom electrode of a memory capacitor in a memory cell includes the step of introducing phosphine gas before introducing silane gas onto a silicon wafer. The introduction of phosphine gas before introduction of silane gas prevents a lower phosphorous concentration portion in the bottom cylindrical bottom electrode, thereby achieving a suitable HSG structure on the cylindrical bottom electrode.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: July 2, 2002
    Assignee: NEC Corporation
    Inventor: Ichiro Yamamoto
  • Publication number: 20020049229
    Abstract: The present invention relates to a compound represented by Formula (I) below: 1
    Type: Application
    Filed: October 4, 2001
    Publication date: April 25, 2002
    Applicant: MOCHIDA PHARMACEUTICAL CO., LTD.
    Inventors: Ichiro Yamamoto, Manabu Itoh, Fumiaki Yamasaki, Yasushige Akada, Yutaka Miyazaki, Shinichi Ogawa
  • Patent number: 6368913
    Abstract: A method of manufacturing a semiconductor device such as a DRAM device having a capacitor. The capacitor has an electrode having an HSG structure. The electrode is formed by: forming a cylinder type electrode body which is made of amorphous silicon and which has at least an inner wall surface and an outer wall surface, the forming a cylinder type electrode body comprises at least forming an amorphous silicon film by using a thermal CVD method; and by forming hemispherical grain (HSG) at least at the inner wall surface and at the outer wall surface of the cylinder type electrode body to form a hemispherically grained cylinder type electrode. When the amorphous silicon film is formed by using a thermal CVD method, at least an initial growth temperature of the amorphous silicon film is controlled to be within a range from 450 to 520 degrees Celsius.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: April 9, 2002
    Assignee: NEC Corporation
    Inventor: Ichiro Yamamoto
  • Publication number: 20010031554
    Abstract: A method for forming hemispherical grains (HSG) on a cylindrical bottom electrode of a memory capacitor in a memory cell includes the step of introducing phosphine gas before introducing silane gas onto a silicon wafer. The introduction of phosphine gas before introduction of silane gas prevents a lower phosphorous concentration portion in the bottom cylindrical bottom electrode, thereby achieving a suitable HSG structure on the cylindrical bottom electrode.
    Type: Application
    Filed: January 29, 1999
    Publication date: October 18, 2001
    Inventor: ICHIRO YAMAMOTO