Patents by Inventor Ichirou Mizuguchi

Ichirou Mizuguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DRAM device
    Patent number: 8941163
    Abstract: A DRAM device includes plural N-channel MIS transistors arranged in a matrix over a P well, and a plurality of capacitors formed corresponding to the plurality of N-channel MIS transistors, and plural word lines formed corresponding to each row of the plurality of N-channel MIS transistors, and a plurality of bit lines formed corresponding to each column of the plurality of N-channel MIS transistors, and a P+ diffusion layer formed extending in the direction that the plurality of word lines extend and supplied with a p well voltage potential.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Ichirou Mizuguchi, Hiroshi Furuta
  • DRAM DEVICE
    Publication number: 20130334582
    Abstract: A DRAM device includes plural N-channel MIS transistors arranged in a matrix over a P well, and a plurality of capacitors formed corresponding to the plurality of N-channel MIS transistors, and plural word lines formed corresponding to each row of the plurality of N-channel MIS transistors, and a plurality of bit lines formed corresponding to each column of the plurality of N-channel MIS transistors, and a P+ diffusion layer formed extending in the direction that the plurality of word lines extend and supplied with a p well voltage potential.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 19, 2013
    Inventors: Ichirou MIZUGUCHI, Hiroshi FURUTA
  • Integrated circuit apparatus
    Patent number: 7274616
    Abstract: An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: September 25, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Hiroshi Furuta, Kenjyu Shimogawa, Ichirou Mizuguchi, Junji Monden, Shinji Takeda
  • Integrated circuit apparatus
    Publication number: 20060164905
    Abstract: An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.
    Type: Application
    Filed: January 3, 2006
    Publication date: July 27, 2006
    Applicant: NEC Electronics Corporation
    Inventors: Hiroshi Furuta, Kenjyu Shimogawa, Ichirou Mizuguchi, Junji Monden, Shinji Takeda