Patents by Inventor IDAN GOLDENBERG
IDAN GOLDENBERG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134696Abstract: Systems and methods for offloading data storage processing tasks from a data storage device to a graphics processing unit data are described. Data storage devices may include a peripheral interface configured to connect to a host system and provide access to a host memory buffer. The data storage device may store task input data to the host memory buffer. The data storage device may notify a processor device including the graphics processing unit to initiate the storage processing task. The processor device may access the task input data from the host memory buffer and store the task output data to the host memory buffer for access by the data storage device.Type: ApplicationFiled: July 17, 2023Publication date: April 25, 2024Inventors: Eran Moshe, Shay Benisty, Idan Goldenberg
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Patent number: 11481271Abstract: A storage system generates a low-density parity check (LDPC) code from a plurality of subcodes. The storage system stores each subcode in a different page of a word line in the memory. The subcode can be stored in one plane in the memory or across multiple planes. When the subcodes are stored across multiple planes, they can be stored in a checkboard pattern.Type: GrantFiled: March 16, 2021Date of Patent: October 25, 2022Assignee: Western Digital Technologies, Inc.Inventors: Eran Sharon, Idan Goldenberg, Idan Alrod, Ran Zamir, Alexander Bazarsky
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Publication number: 20220300369Abstract: A storage system generates a low-density parity check (LDPC) code from a plurality of subcodes. The storage system stores each subcode in a different page of a word line in the memory. The subcode can be stored in one plane in the memory or across multiple planes. When the subcodes are stored across multiple planes, they can be stored in a checkboard pattern.Type: ApplicationFiled: March 16, 2021Publication date: September 22, 2022Applicant: Western Digital Technologies, Inc.Inventors: Eran Sharon, Idan Goldenberg, Idan Alrod, Ran Zamir, Alexander Bazarsky
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Patent number: 11289172Abstract: Calibration of soft bit reference levels in a non-volatile memory system is disclosed. A set of memory cells are sensed at a hard bit reference level and test soft bit reference levels. The test soft bit reference levels are grouped around the hard bit reference level. A metric is determined for the test soft bit reference levels. Bins are defined based on the hard bit reference level and the set of test soft bit reference levels. A metric may be determined for each of the bins. The new soft bit reference levels are determined based on the metric. In one aspect, the metric is how many memory cells have a value for a physical parameter within each bin. The soft bit reference levels may be established based on a target percentage for the bins. In one aspect, the metric is how many unsatisfied counters are within each bin.Type: GrantFiled: February 9, 2021Date of Patent: March 29, 2022Assignee: Western Digital Technologies, Inc.Inventors: Ran Zamir, Eran Sharon, Idan Goldenberg
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Publication number: 20220051746Abstract: Calibration of soft bit reference levels in a non-volatile memory system is disclosed. A set of memory cells are sensed at a hard bit reference level and test soft bit reference levels. The test soft bit reference levels are grouped around the hard bit reference level. A metric is determined for the test soft bit reference levels. Bins are defined based on the hard bit reference level and the set of test soft bit reference levels. A metric may be determined for each of the bins. The new soft bit reference levels are determined based on the metric. In one aspect, the metric is how many memory cells have a value for a physical parameter within each bin. The soft bit reference levels may be established based on a target percentage for the bins. In one aspect, the metric is how many unsatisfied counters are within each bin.Type: ApplicationFiled: February 9, 2021Publication date: February 17, 2022Applicant: Western Digital Technologies, Inc.Inventors: Ran Zamir, Eran Sharon, Idan Goldenberg
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Patent number: 11190219Abstract: An error correcting code (ECC) decoder for a non-volatile memory device is configured to decode data stored by the non-volatile memory device using a parity check matrix with columns of different column weights. The ECC decoder is further configured to artificially slow processing of one or more of the columns of the parity check matrix in response to column weights for the one or more columns satisfying a threshold.Type: GrantFiled: June 30, 2020Date of Patent: November 30, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Ran Zamir, Dudy Avraham, Eran Sharon, Idan Alrod, Idan Goldenberg, Omer Fainzilber, Yuri Ryabinin, Yan Dumchin, Igal Mariasin, Eran Banani
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Patent number: 10979072Abstract: A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.Type: GrantFiled: March 19, 2019Date of Patent: April 13, 2021Assignee: Western Digital Technologies, Inc.Inventors: Ran Zamir, Eran Sharon, Idan Goldenberg, Dudy David Avraham
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Publication number: 20200304149Abstract: A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.Type: ApplicationFiled: March 19, 2019Publication date: September 24, 2020Applicant: Western Digital Technologies, Inc.Inventors: Ran Zamir, Eran Sharon, Idan Goldenberg, Dudy David Avraham
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Patent number: 10567001Abstract: In an illustrative example, a method includes sensing at least a portion of a representation of a convolutional low-density parity-check (CLDPC) codeword stored at a memory of a data storage device. The method further includes receiving the portion of the representation of the CLDPC codeword at a controller of the data storage device. The method further includes performing one or more management operations associated with the memory based on an estimated number of errors of the portion of the representation of the CLDPC codeword.Type: GrantFiled: July 30, 2018Date of Patent: February 18, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Idan Goldenberg, Ishai Ilani, Alexander Bazarsky, Rami Rom
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Patent number: 10389389Abstract: In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.Type: GrantFiled: June 8, 2017Date of Patent: August 20, 2019Assignee: Western Digital Technologies, Inc.Inventors: Idan Goldenberg, Stella Achtenberg, Alexander Bazarsky, Eran Sharon, Karin Inbar, Michael Ionin
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Patent number: 10372539Abstract: A black box recorder for an autonomous vehicle includes an interface configured to receive data from an engine control unit (ECU) device. The data includes first data and second data. The black box recorder further includes an error correction code (ECC) engine configured to determine a first parity size associated with the first data based on a characteristic of the first data and a second parity size associated with the second data based on a characteristic of the second data. The first parity size is different than the second parity size. The ECC engine is further configured to generate a convolutional low-density parity-check (CLDPC) codeword that includes the first data, the second data, first redundancy data associated with the first data, and second redundancy data associated with the second data. The first redundancy data has the first parity size, and the second redundancy data has the second parity size.Type: GrantFiled: November 20, 2017Date of Patent: August 6, 2019Assignee: Western Digital Technologies, Inc.Inventors: David Avraham, Idan Goldenberg, Alexander Bazarsky, Eyal Sobol, Martin Booth
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Patent number: 10367528Abstract: In an illustrative example, a method includes receiving data to be processed in accordance with a convolutional low-density parity-check (CLDPC) code. The method also includes processing the data based on a parity check matrix associated with the CLDPC code. The parity check matrix includes a first portion and a second portion. The first portion includes a plurality of copies of a first sub-matrix that is associated with a first sub-code, and the second portion includes a copy of second sub-matrix that is associated with a second sub-code.Type: GrantFiled: June 10, 2016Date of Patent: July 30, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Idan Goldenberg, Alexander Bazarsky, Stella Achtenberg, Ishai Ilani, Eran Sharon
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Patent number: 10355712Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.Type: GrantFiled: March 31, 2017Date of Patent: July 16, 2019Assignee: SanDisk Technologies LLCInventors: Rami Rom, Idan Goldenberg, Alexander Bazarsky, Eran Sharon, Ran Zamir, Idan Alrod, Stella Achtenberg
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Publication number: 20190155687Abstract: A black box recorder for an autonomous vehicle includes an interface configured to receive data from an engine control unit (ECU) device. The data includes first data and second data. The black box recorder further includes an error correction code (ECC) engine configured to determine a first parity size associated with the first data based on a characteristic of the first data and a second parity size associated with the second data based on a characteristic of the second data. The first parity size is different than the second parity size. The ECC engine is further configured to generate a convolutional low-density parity-check (CLDPC) codeword that includes the first data, the second data, first redundancy data associated with the first data, and second redundancy data associated with the second data. The first redundancy data has the first parity size, and the second redundancy data has the second parity size.Type: ApplicationFiled: November 20, 2017Publication date: May 23, 2019Inventors: DAVID AVRAHAM, IDAN GOLDENBERG, ALEXANDER BAZARSKY, EYAL SOBOL, MARTIN BOOTH
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Patent number: 10289341Abstract: Systems and methods are described for generating location-based read voltage offsets in a data storage device. Optimal read voltage thresholds vary across memory elements of a device. However, data storage devices are often limited in the number of read voltage thresholds that can be maintained in the device. Thus, it may not be possible to maintain optimal read voltage parameters for each memory element within a device. The systems and methods described herein provide for increased accuracy of read voltage thresholds when applied to memory elements within a specific location in a device, by enabling the use of location-based read voltage offsets, depending on a relative location of the memory element being read from. The read voltage offsets can be determined based on application of a neural network to data regarding optimal read voltage thresholds determined from at least a sample of memory elements in a device.Type: GrantFiled: June 30, 2017Date of Patent: May 14, 2019Assignee: Western Digital Technologies, Inc.Inventors: Roi Kirshenbaum, Karin Inbar, Idan Goldenberg, Nian Niles Yang, Rami Rom, Alexander Bazarsky, Ariel Navon, Philip David Reusswig
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Patent number: 10290347Abstract: Systems and methods are described for compacting operating parameter sets in a data storage device. Data storage device may be configured to maintain multiple operating parameter sets, each of which stores various parameters for interacting with different memory elements within the device. The data storage device may further be limited in the total number of operating parameter sets that can be maintained in the device at any given time. Thus, the data storage device may be required at various times to combine two or more operating parameter sets, to enable creation of a new operating parameter set. Because each operating parameter set can contain a number of parameters, identification of similar sets for combination can be computationally intensive. To identify similar sets in an efficient manner, a device as disclosed herein is enabled to reduce a dimensionality of each set, and locate similar sets under that reduced dimensionality.Type: GrantFiled: June 30, 2017Date of Patent: May 14, 2019Assignee: Western Digital Technologies, Inc.Inventors: Roi Kirshenbaum, Karin Inbar, Idan Goldenberg, Nian Niles Yang, Rami Rom, Alexander Bazarsky, Ariel Navon, Philip David Reusswig
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Patent number: 10236909Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.Type: GrantFiled: March 31, 2017Date of Patent: March 19, 2019Assignee: SanDisk Technologies LLCInventors: Rami Rom, Idan Goldenberg, Alexander Bazarsky, Eran Sharon, Ran Zamir, Idan Alrod, Stella Achtenberg
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Patent number: 10230395Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.Type: GrantFiled: March 31, 2017Date of Patent: March 12, 2019Assignee: SanDisk Technologies LLCInventors: Rami Rom, Idan Goldenberg, Alexander Bazarsky, Eran Sharon, Ran Zamir, Idan Alrod, Stella Achtenberg
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Patent number: 10218384Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.Type: GrantFiled: December 1, 2016Date of Patent: February 26, 2019Assignee: SanDisk Technologies LLCInventors: Eran Sharon, Idan Goldenberg, Ishai Ilani, Idan Alrod, Yuri Ryabinin, Yan Dumchin, Mark Fiterman, Ran Zamir
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Publication number: 20190006003Abstract: Systems and methods are described for compacting operating parameter sets in a data storage device. Data storage device may be configured to maintain multiple operating parameter sets, each of which stores various parameters for interacting with different memory elements within the device. The data storage device may further be limited in the total number of operating parameter sets that can be maintained in the device at any given time. Thus, the data storage device may be required at various times to combine two or more operating parameter sets, to enable creation of a new operating parameter set. Because each operating parameter set can contain a number of parameters, identification of similar sets for combination can be computationally intensive. To identify similar sets in an efficient manner, a device as disclosed herein is enabled to reduce a dimensionality of each set, and locate similar sets under that reduced dimensionality.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: Roi Kirshenbaum, Karin Inbar, Idan Goldenberg, Nian Niles Yang, Rami Rom, Alexander Bazarsky, Ariel Navon, Philip David Reusswig