Abstract: A computer implemented method for predictive modeling, which includes collecting data relating to properties leased to tenants, including features relating to the properties, the tenants, regional data, national data, or global data. Additional features are derived from the collected data, including additional features relating to the properties or the tenants. Each of the properties of the tenants is labeled to indicate a characteristic of the property or the tenant, where each labeled property or tenant is associated with property-features or tenant-features. A machine-learning based model is trained to predict a parameter a specific property or of a specific tenant, using a first subset of the labeled data. Following the training, and in response to receipt of an indication of a specific property or tenant, a prediction of the parameter for the property or the tenant is obtained from the machine-learning based model, and a report including the prediction is generated.

Abstract: A computer system, computer readable storage medium, and computer-implemented method for generating a test program for a device-under-test (DUT). The method includes transmitting a plurality of uncompiled snippets and a plurality of uncompiled micro-functions into a compiler. The method also includes selecting, randomly, a portion of uncompiled micro-functions from the plurality of uncompiled micro-functions. The method further includes compiling the uncompiled snippets and the portion of uncompiled micro-functions, thereby generating a plurality of compiled snippets and a compiled portion of micro-functions. The method also includes interweaving, randomly, the compiled portion of micro-functions with the plurality of compiled snippets, thereby at least partially generating a test program for the DUT. The method further includes executing one or more post-silicon validation tests for the DUT with the test program.

Abstract: A method for performing an address translation context switch includes initializing a computer processor to a first context by storing information identifying the first context in a control register of the computer processor. The first context specifies a mapping of virtual addresses of instructions to physical memory addresses in a first memory area. Information identifying a second context is stored in a memory address translation independent storage, where the second context specifies mapping of virtual addresses of instructions to physical memory addresses in a second memory area. The information identifying the second context is written to the control register of the computer processor.

Abstract: A computer system, computer readable storage medium, and computer-implemented method for generating a test program for a device-under-test (DUT). The method includes transmitting a plurality of uncompiled snippets and a plurality of uncompiled micro-functions into a compiler. The method also includes selecting, randomly, a portion of uncompiled micro-functions from the plurality of uncompiled micro-functions. The method further includes compiling the uncompiled snippets and the portion of uncompiled micro-functions, thereby generating a plurality of compiled snippets and a compiled portion of micro-functions. The method also includes interweaving, randomly, the compiled portion of micro-functions with the plurality of compiled snippets, thereby at least partially generating a test program for the DUT. The method further includes executing one or more post-silicon validation tests for the DUT with the test program.

Abstract: A method for performing an address translation context switch includes initializing a computer processor to a first context by storing information identifying the first context in a control register of the computer processor. The first context specifies a mapping of virtual addresses of instructions to physical memory addresses in a first memory area. Information identifying a second context is stored in a memory address translation independent storage, where the second context specifies mapping of virtual addresses of instructions to physical memory addresses in a second memory area. The information identifying the second context is written to the control register of the computer processor.