Patents by Inventor Idan LOTAN

Idan LOTAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High-speed, low power, low kickback noise comparator suitable for a multi-comparator successive approximation analog-to-digital converter (ADC)
    Patent number: 10855305
    Abstract: A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Roee Eitan, Ahmad B. Khairi, Yosi Sanhedrai, Ram Livne, Ilya Kraimer, Hen Sallem, Idan Lotan, Ariel Cohen, Dror Lazar
  • HIGH-SPEED, LOW POWER, LOW KICKBACK NOISE COMPARATOR SUITABLE FOR A MULTI-COMPARATOR SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC)
    Publication number: 20190238150
    Abstract: A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit.
    Type: Application
    Filed: April 4, 2019
    Publication date: August 1, 2019
    Inventors: Roee EITAN, Ahmad B. KHAIRI, Yosi SANHEDRAI, Ram LIVNE, Ilya KRAIMER, Hen SALLEM, Idan LOTAN, Ariel COHEN, Dror LAZAR