Patents by Inventor Idan Matari

Idan Matari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11558316
    Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: January 17, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Liron Mula, Idan Matari, Niv Aibester, George Elias, Lion Levi
  • Publication number: 20220263776
    Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.
    Type: Application
    Filed: February 15, 2021
    Publication date: August 18, 2022
    Inventors: Liron Mula, Idan Matari, Niv Aibester, George Elias, Lion Levi
  • Patent number: 11252027
    Abstract: A network element includes a plurality of ports, multiple computational modules, configurable forwarding circuitry and a central block. The ports include child ports coupled to child network elements or network nodes and parent ports coupled to parent network elements. The computational modules collectively perform a data reduction operation of a data reduction protocol. The forwarding circuitry interconnects among ports and computational modules. The central block receives a request indicative of child ports, a parent port, and computational modules required for performing reduction operations on data received via the child ports, for producing reduced data destined to the parent port, to derive from the request a topology that interconnects among the child ports, parent port and computational modules for performing the data reduction operations and to forward the reduced data for transmission to the selected parent port, and to configure the forwarding circuitry to apply the topology.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: February 15, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Ortal Ben-Moshe, Lion Levi, Itamar Rabenstein, Idan Matari, Noam Michaelis, Ofir Merdler, Evyatar Romlet
  • Publication number: 20210234753
    Abstract: A network element includes a plurality of ports, multiple computational modules, configurable forwarding circuitry and a central block. The ports include child ports coupled to child network elements or network nodes and parent ports coupled to parent network elements. The computational modules collectively perform a data reduction operation of a data reduction protocol. The forwarding circuitry interconnects among ports and computational modules. The central block receives a request indicative of child ports, a parent port, and computational modules required for performing reduction operations on data received via the child ports, for producing reduced data destined to the parent port, to derive from the request a topology that interconnects among the child ports, parent port and computational modules for performing the data reduction operations and to forward the reduced data for transmission to the selected parent port, and to configure the forwarding circuitry to apply the topology.
    Type: Application
    Filed: January 23, 2020
    Publication date: July 29, 2021
    Inventors: Ortal Ben-Moshe, Lion Levi, Itamar Rabenstein, Idan Matari, Noam Michaelis, Ofir Merdler, Evyatar Romlet
  • Publication number: 20210042251
    Abstract: A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.
    Type: Application
    Filed: August 11, 2019
    Publication date: February 11, 2021
    Inventors: Lion Levi, Aviv Kfir, Idan Matari, Ran Shani, Zachy Haramaty, Nir Monovich, Matty Kadosh
  • Patent number: 10915479
    Abstract: A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.
    Type: Grant
    Filed: August 11, 2019
    Date of Patent: February 9, 2021
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Lion Levi, Aviv Kfir, Idan Matari, Ran Shani, Zachy Haramaty, Nir Monovich, Matty Kadosh