Patents by Inventor Idan Rozenberg
Idan Rozenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11743201Abstract: Electronic apparatus includes functional circuitry configured to respond to requests from a plurality of client devices, data storage circuitry configured as a plurality of client queues in which each respective client queue is configured to store pending requests from a respective client device, priority determination circuitry configured to assign a respective priority level to each respective client queue based at least in part on requests stored in the respective client queues, and arbiter circuitry configured to control access to the functional circuitry by the plurality of client devices. The arbiter circuitry is configured to monitor the priority level of each respective client queue, and control passage of requests from client queues to the functional circuitry based at least in part on a respective priority level assigned to each respective client queue. The priority determination circuitry includes fill level detector circuitry configured to determine a fill level of each client queue.Type: GrantFiled: August 7, 2020Date of Patent: August 29, 2023Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Yaniv Azulay, Ori Goren, Idan Rozenberg
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Patent number: 10104003Abstract: Aspects of the disclosure provide a method for packet processing. The method includes receiving a plurality of packets at a port of a network device. The plurality of packets belong to a packet flow having a sequence within a stream of packets. The method then includes mapping identifications respectively allocated to the plurality of packets into a data structure of ordered identifications to maintain the sequence, and generating a new packet instance during processing of a specific packet. The specific packet has a specific identification and is one of the plurality of the packets. Then, the method includes inserting a new identification allocated to the new packet instance into the data structure of ordered identifications next to the specific identification to maintain the sequence and transmitting the plurality of packets and the new packet instance from the network device according to the sequence maintained in the data structure.Type: GrantFiled: June 17, 2016Date of Patent: October 16, 2018Assignee: MARVELL ISRAEL (M.I.S.L) LTD.Inventors: Shai Savir, Idan Rozenberg, Eran Blich
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Patent number: 9672042Abstract: A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.Type: GrantFiled: May 29, 2012Date of Patent: June 6, 2017Assignee: NXP USA, INC.Inventors: Roy Glasner, Itzhak Barak, Yuval Peled, Idan Rozenberg, Lev Vaskevich
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Patent number: 9606802Abstract: A processor system is adapted to carry out a predicate swap instruction of an instruction set to swap, via a data pathway, predicate data in a first predicate data location of a predicate register with data in a corresponding additional predicate data location of a first additional predicate data container and to swap, via a data pathway, predicate data in a second predicate storage location of the predicate register with data in a corresponding additional predicate data location in a second additional predicate data container.Type: GrantFiled: March 25, 2011Date of Patent: March 28, 2017Assignee: NXP USA, INC.Inventors: Yuval Peled, Itzhak Barak, Uri Dayan, Amir Kleen, Idan Rozenberg
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Patent number: 9471321Abstract: There is provided a method for controlling fetch-ahead of Fetch Sets into a decoupling First In First Out (FIFO) buffer of a Variable Length Execution Set (VLES) processor architecture, wherein a Fetch Set comprises at least a portion of a VLES group available for dispatch to processing resources within the VLES processor architecture, comprising, for each cycle, determining a number of VLES groups available for dispatch from previously pre-fetched Fetch Sets, and only requesting a fetch-ahead of a next Fetch Set in the next cycle if one of a select set of criteria related to the number of VLES groups available for dispatch is true.Type: GrantFiled: March 30, 2011Date of Patent: October 18, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Lev Vaskevich, Mark Elnekave, Yuval Peled, Idan Rozenberg
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Publication number: 20150082005Abstract: A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.Type: ApplicationFiled: May 29, 2012Publication date: March 19, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Roy Glasner, Itzhak Barak, Yuval Feled, Idan Rozenberg, Lev Vaskevich
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Publication number: 20140025931Abstract: There is provided a method for controlling fetch-ahead of Fetch Sets into a decoupling First In First Out (FIFO) buffer of a Variable Length Execution Set (VLES) processor architecture, wherein a Fetch Set comprises at least a portion of a VLES group available for dispatch to processing resources within the VLES processor architecture, comprising, for each cycle, determining a number of VLES groups available for dispatch from previously pre-fetched Fetch Sets, and only requesting a fetch-ahead of a next Fetch Set in the next cycle if one of a select set of criteria related to the number of VLES groups available for dispatch is true.Type: ApplicationFiled: March 30, 2011Publication date: January 23, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Lev Vaskevich, Mark Elnekave, Yuval Peled, Idan Rozenberg
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Publication number: 20140013087Abstract: A processor system is adapted to carry out a predicate swap instruction of an instruction set to swap, via a data pathway, predicate data in a first predicate data location of a predicate register with data in a corresponding additional predicate data location of a first additional predicate data container and to swap, via a data pathway, predicate data in a second predicate storage location of the predicate register with data in a corresponding additional predicate data location in a second additional predicate data container.Type: ApplicationFiled: March 25, 2011Publication date: January 9, 2014Applicant: Freescale Semiconductor, IncInventors: Yuval Peled, Itzhak Barak, Uri Dayan, Amir Kleen, Idan Rozenberg
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Publication number: 20130326200Abstract: An integrated circuit device comprising at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction. Wherein, the instruction processing module is further arranged to proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register, and to load the validation data into the target register if the validation data does not match the stored data within the target register.Type: ApplicationFiled: February 11, 2011Publication date: December 5, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Amir Kleen, Itzhak Barak, Yuval Peled, Idan Rozenberg, Doron Schupper
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Publication number: 20130290686Abstract: An integrated circuit device comprises at least one instruction processing module arranged to perform branch predication. The at least one instruction processing module comprises at least one predicate calculation module arranged to receive as an input at least one result vector for a predicate function and at least one conditional parameter value therefor and output a predicate result value from the at least one result vector based at least partly on the at least one received conditional parameter value.Type: ApplicationFiled: January 21, 2011Publication date: October 31, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Yuval Peled, Itzhak Barak, Idan Rozenberg, Doron Schupper, Lev Vaskevich
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Patent number: 8533441Abstract: A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle.Type: GrantFiled: August 12, 2008Date of Patent: September 10, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Yuval Peled, Itzhak Barak, Uri Dayan, Idan Rozenberg, Yoram Salant
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Patent number: 8332620Abstract: A method for executing an instruction, the method includes: executing a compare and configure mask instruction, wherein the executing comprises: performing a comparison to provide a comparison result; and configuring, in response to the comparison result, a multiple bit mask that is stored in a multiple-purpose register; wherein all bits of the multiple bit mask are configured to have the same value; and applying an algorithmic operation on the multiple bit mask to provide an algorithmic operation result; wherein the algorithmic operation result represents an outcome of a high level programming language conditional statement.Type: GrantFiled: July 25, 2008Date of Patent: December 11, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Uri Dayan, Aviram Amir, Itzhaki Barak, Shahar Nahum, Idan Rozenberg, Ron Shaposhnikov, Erez Steinberg
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Method for executing an instruction loop and a device having instruction loop execution capabilities
Patent number: 8266414Abstract: A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit.Type: GrantFiled: August 19, 2008Date of Patent: September 11, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Lev Vaskevich, Itzhak Barak, Amir Paran, Yuval Peled, Idan Rozenberg, Doron Schupper -
Patent number: 7930522Abstract: A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.Type: GrantFiled: August 19, 2008Date of Patent: April 19, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Guy Shumeli, Itzhak Barak, Uri Dayan, Amir Paran, Idan Rozenberg, Doron Schupper
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Publication number: 20100049954Abstract: A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.Type: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Inventors: Guy Shmueli, Itzhak Barak, Uri Dayan, Amir Paran, Idan Rozenberg, Doron Schupper
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Publication number: 20100049958Abstract: A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit.Type: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Inventors: Lev Vaskevich, Itzhak Barak, Amir Paran, Yuval Peled, Idan Rozenberg, Doron Schupper
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Publication number: 20100042811Abstract: A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle.Type: ApplicationFiled: August 12, 2008Publication date: February 18, 2010Inventors: Yuval Peled, Itzhak Barak, Uri Dayan, Idan Rozenberg, Yoram Salant
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Publication number: 20100023734Abstract: A method for executing an instruction, the method includes: executing a compare and configure mask instruction, wherein the executing comprises: performing a comparison to provide a comparison result; and configuring, in response to the comparison result, a multiple bit mask that is stored in a multiple-purpose register; wherein all bits of the multiple bit mask are configured to have the same value; and applying an algorithmic operation on the multiple bit mask to provide an algorithmic operation result; wherein the algorithmic operation result represents an outcome of a high level programming language conditional statement.Type: ApplicationFiled: July 25, 2008Publication date: January 28, 2010Inventors: Uri Dayan, Aviram Amir, Itzhaki Barak, Shahar Nahum, Idan Rozenberg, Ron Shaposhnikov, Erez Steinberg