Patents by Inventor Idan Saar

Idan Saar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11782726
    Abstract: Approaches in accordance with various embodiments can be used to provide bootstrap data for a computing device, such as a system on chip (SoC). In particular, various embodiments can use one or more shift registers to receive bits of a sequence of bootstrap data in parallel. Individual bits of this bootstrap data sequence can then be provided to the SoC, from the shift register(s), serially and using a single input. Such an approach prevents the need for multiple bootstrap pins on the SoC, as well as the need to multiplex those pins for use with other external devices.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: October 10, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Barak Wasserstrom, Idan Saar, Robert Klein
  • Patent number: 9075764
    Abstract: A multiprocessor system includes a main memory and multiple processing cores that are configured to execute software that uses data stored in the main memory. In some embodiments, the multiprocessor system includes a data streaming unit, which is connected between the processing cores and the main memory and is configured to pre-fetch the data from the main memory for use by the multiple processing cores. In some embodiments, the multiprocessor system includes a scratch-pad processing unit, which is connected to the processing cores and is configured to execute, on behalf of the multiple processing cores, a selected part of the software that causes two or more of the processing cores to access concurrently a given item of data.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: July 7, 2015
    Assignee: APPLE INC.
    Inventor: Idan Saar
  • Publication number: 20120042150
    Abstract: A multiprocessor system includes a main memory and multiple processing cores that are configured to execute software that uses data stored in the main memory. In some embodiments, the multiprocessor system includes a data streaming unit, which is connected between the processing cores and the main memory and is configured to pre-fetch the data from the main memory for use by the multiple processing cores. In some embodiments, the multiprocessor system includes a scratch-pad processing unit, which is connected to the processing cores and is configured to execute, on behalf of the multiple processing cores, a selected part of the software that causes two or more of the processing cores to access concurrently a given item of data.
    Type: Application
    Filed: March 29, 2011
    Publication date: February 16, 2012
    Applicant: PRIMESENSE LTD.
    Inventor: Idan Saar