Patents by Inventor Iddo Amit

Iddo Amit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200243690
    Abstract: A transistor (100), including a planar semiconducting substrate (36), a source (42) formed on the substrate, a first drain (102) formed on the substrate, and a second drain (104) formed on the substrate in a location physically separated from the first drain. At least one gate (38, 40) is formed on the substrate and is configured to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path (62) to be established within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established within the substrate from the source to the second drain.
    Type: Application
    Filed: April 12, 2020
    Publication date: July 30, 2020
    Inventors: Gideon Segev, Iddo Amit, Alexander Henning, Yossi Rosenwaks
  • Patent number: 10707355
    Abstract: A transistor (100), including a planar semiconducting substrate (36), a source (42) formed on the substrate, a first drain (102) formed on the substrate, and a second drain (104) formed on the substrate in a location physically separated from the first drain. At least one gate (38, 40) is formed on the substrate and is configured to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path (62) to be established within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established within the substrate from the source to the second drain.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: July 7, 2020
    Assignee: RAMOT AT TEL AVIV UNIVERSITY LTD.
    Inventors: Gideon Segev, Iddo Amit, Alexander Henning, Yossi Rosenwaks
  • Publication number: 20170243983
    Abstract: A transistor (100), including a planar semiconducting substrate (36), a source (42) formed on the substrate, a first drain (102) formed on the substrate, and a second drain (104) formed on the substrate in a location physically separated from the first drain. At least one gate (38, 40) is formed on the substrate and is configured to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path (62) to be established within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established within the substrate from the source to the second drain.
    Type: Application
    Filed: May 18, 2015
    Publication date: August 24, 2017
    Inventors: Gideon Segev, Iddo Amit, Alexander Henning, Yossi Rosenwaks