Abstract: A digital receiver includes a memory buffer and circuitry. The memory buffer stores samples of an input signal having a sampling rate Fsi. The circuitry includes P filter-families that each includes N filters derived from a prototype Low-Pass Filter (LPF) whose stopband frequency depends on an output sampling rate Fso=?·Fsi. The circuitry is configured to set a sampling time according to Fso, to select, based on the sampling time, multiple filter-families out of the P filter-families, and to construct, based on the N filters in each of the selected filter-families, N interpolated filters that are each aligned to the sampling time. The circuitry is further configured to calculate N filtered samples by applying the N interpolated filters to the samples in the memory buffer, and to generate a sample for an output signal of a frequency-slice of the input signal, by digitally down-converting the N filtered samples.