Patents by Inventor Ido Melamed
Ido Melamed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230418361Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Chen Ranel, Christopher J. Lake, Hem Doshi, Ido Melamed, Vijay Degalahal, Yevgeni Sabin, Reena Patel, Yoav Ben-Raphael, Nimrod Angel, Efraim Rotem, Shaun Conrad, Tomer Ziv, Nir Rosenzweig, Esfir Natanzon, Yoni Aizik, Arik Gihon, Natanel Abitan
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Patent number: 11789516Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.Type: GrantFiled: May 22, 2020Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Chen Ranel, Christopher J. Lake, Hem Doshi, Ido Melamed, Vijay Degalahal, Yevgeni Sabin, Reena Patel, Yoav Ben-Raphael, Nimrod Angel, Efraim Rotem, Shaun Conrad, Tomer Ziv, Nir Rosenzweig, Esfir Natanzon, Yoni Aizik, Arik Gihon, Natanel Abitan
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Patent number: 11543878Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.Type: GrantFiled: May 1, 2018Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Efraim Rotem, Eliezer Weissmann, Eric Dehaemer, Alexander Gendler, Nadav Shulman, Krishnakanth Sistla, Nir Rosenzweig, Ankush Varma, Ariel Szapiro, Arye Albahari, Ido Melamed, Nir Misgav, Vivek Garg, Nimrod Angel, Adwait Purandare, Elkana Korem
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Publication number: 20220179473Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.Type: ApplicationFiled: May 22, 2020Publication date: June 9, 2022Applicant: Intel CorporationInventors: Chen Ranel, Christopher J. Lake, Hem Doshi, Ido Melamed, Vijay Degalahal, Yevgeni Sabin, Reena Patel, Yoav Ben-Raphael, Nimrod Angel, Efraim Rotem, Shaun Conrad, Tomer Ziv, Nir Rosenzweig, Esfir Natanzon, Yoni Aizik, Arik Gihon, Natanel Abitan
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Patent number: 11042213Abstract: Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.Type: GrantFiled: March 30, 2019Date of Patent: June 22, 2021Assignee: Intel CorporationInventors: Alexander Gendler, Yoni Aizik, Chen Ranel, Ido Melamed, Edward Vaiberman
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Publication number: 20210018971Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.Type: ApplicationFiled: May 1, 2018Publication date: January 21, 2021Inventors: EFRAIM ROTEM, ELIEZER WEISSMANN, ERIC DEHAEMER, ALEXANDER GENDLER, NADAV SHULMAN, KRISHNAKANTH SISTLA, NIR ROSENZWEIG, ANKUSH VARMA, ARIEL SZAPIRO, ARYE ALBAHARI, IDO MELAMED, NIR MISGAV, VIVEK GARG, NIMROD ANGEL, ADWAIT PURANDARE, ELKANA KOREM
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Publication number: 20200310527Abstract: Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.Type: ApplicationFiled: March 30, 2019Publication date: October 1, 2020Inventors: Alexander Gendler, Yoni Aizik, Chen Ranel, Ido Melamed, Edward Vaiberman
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Patent number: 10379904Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.Type: GrantFiled: August 31, 2016Date of Patent: August 13, 2019Assignee: Intel CorporationInventors: Eliezer Weissmann, Israel Hirsh, Efraim Rotem, Doron Rajwan, Avinash N. Ananthakrishnan, Natanel Abitan, Ido Melamed, Guy M. Therien
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Patent number: 10345889Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: GrantFiled: August 4, 2017Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
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Publication number: 20180120924Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: ApplicationFiled: August 4, 2017Publication date: May 3, 2018Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
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Publication number: 20180060123Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.Type: ApplicationFiled: August 31, 2016Publication date: March 1, 2018Inventors: Eliezer Weissmann, Israel Hirsh, Efraim Rotem, Doron Rajwan, Avinash N. Ananthakrishnan, Natanel Abitan, Ido Melamed, Guy M. Therien
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Patent number: 9760158Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: GrantFiled: June 6, 2014Date of Patent: September 12, 2017Assignee: Intel CorporationInventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
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Publication number: 20150355705Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: ApplicationFiled: June 6, 2014Publication date: December 10, 2015Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon