Abstract: A method and system for execution of a compiler add-on for securing code are provided. The method includes receiving from a compiler a code in machine language; generating at least one validator code for protection of the received code; generating at least one execution proof for protection of at least one execution flow of the received code; embedding the at least validator code and at least one execution proof into the received code to create a protected code; and storing the protected code in a storage.

Abstract: A computing system and method for attestation of secured code, data and execution flows are provided. The computing system includes a processing circuitry; a memory communicatively connected to the processing circuity, the memory containing therein a protected code; and a protector circuitry connected to the processing circuitry; such that upon execution of the protected code by the processing circuitry the computing system is configured to: initialize the protector engine; perform at least one static protection check using the protector circuitry; perform at least one dynamic protection checks using the protector circuitry; and generate a notification upon detection of an error in any one the at least one static check and the at least one dynamic check.

Abstract: A secure processing engine and method configured to protect a computing system are provided. The system includes a first processor configured to provide real-time protection to at least processes executed over the main processor of the protected computing system; and a direct memory access (DMA) configured to provide an access to a main memory of the main processor, wherein the first processor is coupled to the DMA and further configured to monitor the at least processes by accessing the main memory via the DMA; wherein the first processor operates in an execution environment in complete isolation from an execution environment of the main processor.

Abstract: A secure processing engine and method configured to protect a computing system are provided. The system includes a first processor configured to provide real-time protection to at least processes executed over the main processor of the protected computing system; and a direct memory access (DMA) configured to provide an access to a main memory of the main processor, wherein the first processor is coupled to the DMA and further configured to monitor the at least processes by accessing the main memory via the DMA; wherein the first processor operates in an execution environment in complete isolation from an execution environment of the main processor.

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).