Abstract: Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.

Abstract: Embodiments of the present invention disclose a method, a computer program product, and a computer system for system for executing instructions, comprising a processor to detect a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. In addition, the processor can also execute the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. Furthermore, the processor can execute additional instructions based on the result of the pair of destructive instructions stored in the shared physical register.

Abstract: Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.

Abstract: A memory array includes m·(n+1) memory cells, wherein n and m are natural numbers greater than zero. Each of the plurality of memory cells is connected to one of (n+1) bitlines and one of m wordlines. The memory array further includes n outputs configured for reading a content of the memory array. The memory array further includes n output switches, wherein an i-th output switch is configured for selectively connecting, in response to a switching signal, either an i-th bitline or an (i+1)-th bitline to an i-th output, and wherein i is a natural number and 0?i?n?1. The memory array further includes an (n+1)-th output switch, wherein the (n+1)-th output switch is configured for selectively connecting, in response to the switching signal, either the (n+1)-th bitline or a defined potential to an (n+1)-th output.