Abstract: A storage device includes: a memory device; and a memory controller configured to receive, from an external device having an external memory, a write command for storing data in the memory device and address information of an area in the external memory that corresponds to the write command, and acquire write data from the external device based on the address information. The memory controller may be further configured to store the write data in the memory device in response to the write command. The memory controller may be further configured to acquire a portion of the write data from the external memory upon a failure of storage of the portion of the write data in the memory device, and provide a response to the write command to the external device after completing storing of the write data in the memory device.

Abstract: A controller controls an operation of a semiconductor memory device based on a request received from a host. The controller includes a host interface, a first function block, a second function block, and an internal command cache. The host interface generates a first internal command in response to the request. The first function block generates a second internal command in response to the first internal command. The second function block operates in response to the second internal command. The internal command cache caches at least one internal command corresponding to a reference internal command.

Abstract: A data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2N, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is N, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not N.

Abstract: A memory controller includes a plurality of processors, a memory device and a memory manager. The memory device includes a plurality of segments, which are divided into a plurality of segment groups, to which group identifiers are respectively assigned. The memory manager is configured to map a first buffer identifier to a first group identifier from among the group identifiers, select one or more segments only from a first segment group, to which the first group identifier is assigned among the plurality of segment groups, map the first buffer identifier to the one or more segments, and allocate, to a first processor from among the plurality of processors, the first buffer identifier and the one or more segments.

Abstract: A storage device may input a program command requesting to program target data into the memory, input the target data into a memory, and input the program confirmation command into the memory after inputting the program command and the target data into the memory. In this case, the program confirmation command may include information about a cell type of memory cells to be programmed with target data among a plurality of memory cells.

Abstract: A storage device includes: a memory device; and a memory controller configured to receive, from an external device having an external memory, a write command for storing data in the memory device and address information of an area in the external memory that corresponds to the write command, and acquire write data from the external device based on the address information. The memory controller may be further configured to store the write data in the memory device in response to the write command. The memory controller may be further configured to acquire a portion of the write data from the external memory upon a failure of storage of the portion of the write data in the memory device, and provide a response to the write command to the external device after completing storing of the write data in the memory device.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2N, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is N, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not N.

Abstract: A storage device may input a program command requesting to program target data into the memory, input the target data into a memory, and input the program confirmation command into the memory after inputting the program command and the target data into the memory. In this case, the program confirmation command may include information about a cell type of memory cells to be programmed with target data among a plurality of memory cells.

Abstract: A device for implementing a storage architecture includes a front-end chip having at least one front-end link, and at least one back-end chip having back-end link for communication with the front-end link. The front-end link and the back-end link include a link layer and a physical layer, respectively. A data packet that is transmitted between the front-end link and the back-end link is composed of at least one flow control digit, and the flow control digit is composed of at least one physical digit. The link layer is configured to process data in the form of separating the flow control digit into upper layer data and flow control data. And the physical layer is configured to process data in the form of a data packet part and a control packet part.

Abstract: A storage device includes a memory device including one or more memory blocks including first sub-areas and second sub-areas configured to store higher level data than the first sub-areas, and a controller configured to use the first sub-areas before the second sub-areas in order to store data in the memory device.

Abstract: A data receiving circuit includes a forwarded fast clock domain configured to output data transmitted from a data transmitting circuit in synchronization with a forwarded fast clock signal, and a local clock domain configured to generate a synchronized fetch enable signal in synchronization with a local fast clock signal and output the data transmitted from the forwarded fast clock domain in synchronization with a local slow clock.

Abstract: Provided herein may be a storage device for supporting dynamic allocation of memory and a method of operating the same. The storage device may include a plurality of memory dies, a state detector configured to detect respective memory states of the plurality of memory dies, a memory information storage configured to store defect information that is information about memory dies in which defects have occurred among the plurality of memory dies, and a memory controller configured to, in response to a memory die allocation request for performing an operation corresponding to an externally provided operation request, determine allocation of a memory die based on a result of comparison between each detected memory state and the defect information.

Abstract: A data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2N, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is N, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not N.

Abstract: A data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2N, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is N, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not N.

Abstract: A data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2N, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is N, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not N.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device including a plurality of zones, a memory device including a plurality of zones; a buffer memory device including a plurality of slots; and a memory controller including a plurality of zone buffers respectively corresponding to the plurality of zones. The memory controller may store write data in one or more of the plurality of slots, store map data corresponding to the write data in a zone buffer that corresponds to a zone in which the write data is to be stored, and then store the write data, which is stored in the one or more slots, in the zone corresponding to the zone buffer based on the map data stored in the zone buffer.

Abstract: Provided is a method by which a second chip obtains a control code such as firmware in a memory controller having a chiplet-based structure. The memory controller includes a first chip configured to perform a first operation, a plurality of second chips configured to perform a second operation, a plurality of data links configured to connect the first chip and each of the plurality of second chips on a one-to-one basis and used for data transmission between the first chip and each of the plurality of second chips during normal operation after booting, a control link connected to the first chip and all the plurality of second chips and used to transmit a control code for performing the second operation of the plurality of second chips, and a memory connected to the first chip to store the control code of the plurality of second chips.

Abstract: A storage device may input a program command requesting to program target data into the memory, input the target data into a memory, and input the program confirmation command into the memory after inputting the program command and the target data into the memory. In this case, the program confirmation command may include information about a cell type of memory cells to be programmed with target data among a plurality of memory cells.