Patents by Inventor Ifeanyi Okafor

Ifeanyi Okafor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BARRIER DISPENSING COMBINED WITH NON-CONDUCTIVE PASTE TO ENABLE PACKAGES WITH RESTRICTED UNDERFILL AREAS
    Publication number: 20240321807
    Abstract: Embodiments disclosed herein include multi-die modules. In an embodiment, the multi-die module comprises a first die and a second die coupled to the first die. In an embodiment, the second die comprises a keep out zone that at least partially overlaps the first die. The multi-die module may further comprise an underfill between the first die and the second die. In an embodiment, the underfill is entirely outside the keep out zone, and an edge of the underfill facing the keep out zone is non-vertical.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 26, 2024
    Inventors: Jonas CROISSANT, Xavier F. BRUN, Gustavo BELTRAN, Roberto SERNA, Ye Seul NAM, Timothy GOSSELIN, Jesus S. NIETO PESCADOR, Dingying David XU, John C. DECKER, Ifeanyi OKAFOR, Yiqun BAI
  • Barrier structures for underfill containment
    Patent number: 12002727
    Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: June 4, 2024
    Assignee: Intel Corporation
    Inventors: Ziyin Lin, Vipul Mehta, Wei Li, Edvin Cetegen, Xavier Brun, Yang Guo, Soud Choudhury, Shan Zhong, Christopher Rumer, Nai-Yuan Liu, Ifeanyi Okafor, Hsin-Wei Wang
  • BARRIER STRUCTURES FOR UNDERFILL CONTAINMENT
    Publication number: 20210249322
    Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Vipul Mehta, Wei Li, Edvin Cetegen, Xavier Brun, Yang Guo, Soud Choudhury, Shan Zhong, Christopher Rumer, Nai-Yuan Liu, Ifeanyi Okafor, Hsin-Wei Wang