Abstract: A method of selecting a software code optimisation for a section of algorithm software code in order to modify resource usage of hardware, the method comprising the steps of classifying each of a plurality of software code optimisations each characterising modifications to the section of software code that modify the hardware resource usage, forming combinations of the software code optimisations, each containing at least two of the software code optimisations and being formed according to an interdependency of the optimisation techniques of the software code optimisations in the combination, wherein the software code optimisations of each combination are useable together, and modifying the section of software code with at least two of the software code optimisations belonging to a selected combination of the set of combinations in order to modify the resource usage of the hardware executing the section of software code.

Abstract: An automated test equipment includes a test processor configured to provide a signal to a device under test on the basis of a sequence of instructions defining an evaluation of test vectors. The test processor is configured to map a test vector onto a set of signal states or signal transitions. Furthermore, the test processor is configured to variably select a number of signal states or signal transitions provided in the signal based on a current test vector in dependence on a current instruction.

Abstract: A method of configuring a System-on-Chip (SoC) to execute a Convolutional Neural Network (CNN) by (i) receiving scheduling schemes each specifying a sequence of operations executable by Processing Units (PUs) of the SoC; (ii) selecting, a scheduling scheme for a current layer of the CNN; (iii) determining a current state of memory for a storage location in the SoC allocated for storing feature map data from the CNN; (iv) selecting, from the plurality of scheduling schemes and dependent upon the scheduling scheme for the current layer of the CNN, a set of candidate scheduling schemes for a next layer of the CNN; and (v) selecting, from the set of candidate scheduling schemes dependent upon the determined current state of memory, a scheduling scheme for the next layer of the CNN.

Abstract: A packaging system for a temperature sensitive payload is provided. The system includes side panels and end panels forming a product compartment. Cooling layers within the product compartment are located below and above the products. Channel members located between the side panels and the payload and between the end panels and the payload create vertical channels having rectangular cross sectional areas for convective air movement.

Abstract: A packaging system for a temperature sensitive payload is provided. The system includes side panels and end panels forming a product compartment. Cooling layers within the product compartment are located below and above the products. Channel members located between the side panels and the payload and between the end panels and the payload create vertical channels having rectangular cross sectional areas for convective air movement.

Abstract: A packaging system for a temperature sensitive payload is provided. The system includes insulative side panels and end panels forming a product compartment. Cooling layers within the product compartment are located below and above the payload. Channel members disposed between the side panels and the payload and between the end panels and the payload create vertical channels for convective air movement.

Abstract: A packaging system for a temperature sensitive payload is provided. The system includes insulative panels, including side panels and end panels, forming a product compartment. Cooling layers within the product compartment are located below and above the payload. Vertical posts disposed between the side panels and the payload and between the end panels and the payload create spaces and channels for convective air movement.

Abstract: System and method for implementing a memory test language compiler. The compiler includes a fast semantic processor for interpreting programming patterns in a test program, including converting stateful patterns into stateless patterns, and a device access timing generation module for generating an output based on the stateless patterns. The fast semantic processor can generate a closure for a device access line as the output. In the state of the closure, each device access line is in a closed state. A functor is formed from the interdependency of the variables and the loop dependency and a cache is used to handle recursive variables. The functor is propagated to device access lines as output, wherein the functor references the cache when needed.

Abstract: An instruction provider for providing a sequence of instructions based on a representation of a sequence of test vectors. Each instruction defines the provision of at least one test vector to a device under test. The instruction provider is configured to identify in the representation of the sequence of test vectors subsequences of test vectors which occur at least two times in the representation of the sequence of test vectors. Furthermore, the instruction provider is configured to store the identified subsequences in a dictionary memory structure and to provide the sequence of instructions such that the sequence of instructions includes at least a first instruction defining a first provision of a first subsequence of test vectors stored in the dictionary memory structure and a second instruction defining a second provision of the first subsequence. The first instruction and the second instruction reference to the same entry of the dictionary memory structure.

Abstract: An automated test equipment includes a test processor configured to provide a signal to a device under test on the basis of a sequence of instructions defining an evaluation of test vectors. The test processor is configured to map a test vector onto a set of signal states or signal transitions. Furthermore, the test processor is configured to variably select a number of signal states or signal transitions provided in the signal based on a current test vector in dependence on a current instruction.

Abstract: A thermally insulated pallet shipper is provided for use in any industry where temperature sensitive products are shipped, including the pharmaceutical, hospital and food industries, particularly for shipping payloads by air. The pallet shipper is made from just four individual foam molded structures: a base, a first corner structure, a second corner structure and a lid.

Abstract: A thermally insulated pallet shipper is provided for use in any industry where temperature sensitive products are shipped, including the pharmaceutical, hospital and food industries, particularly for shipping payloads by air. The pallet shipper is made from just four individual foam molded structures: a base, a first corner structure, a second corner structure and a lid.

Abstract: A thermally insulated pallet shipper is provided for use in any industry where temperature sensitive products are shipped, including the pharmaceutical, hospital and food industries, particularly for shipping payloads by air. The pallet shipper is made from just four individual foam molded structures: a base, a first corner structure, a second corner structure and a lid.

Abstract: A packaging system for a temperature sensitive payload is provided. The system comprises insulative panels, including side panels and end panels, forming a product compartment. Cooling layers within the product compartment are located below and above the products. Channel members affixed to the side panels and/or the end panels create spaces and channels for convective air movement.

Abstract: System and method for implementing a memory test language compiler. The compiler includes a fast semantic processor for interpreting programming patterns in a test program, including converting stateful patterns into stateless patterns, and a device access timing generation module for generating an output based on the stateless patterns. The fast semantic processor can generate a closure for a device access line as the output. In the state of the closure, each device access line is in a closed state. A functor is formed from the interdependency of the variables and the loop dependency and a cache is used to handle recursive variables. The functor is propagated to device access lines as output, wherein the functor references the cache when needed.

Abstract: A packaging system for a temperature sensitive payload is provided. The system comprises insulative panels, including side panels and end panels, forming a product compartment. Cooling layers within the product compartment are located below and above the products. Vertical posts disposed between the side panels and the payload and between the end panels and the payload create spaces and channels for convective air movement.

Abstract: A device for controlling data communication flow to a data buffer of an integrated circuit is disclosed. The device receives data communicated from a transmitting device. The received data is placed in a data buffer in memory. The data buffer is defined by a set of buffer descriptors, whereby a number of free buffer descriptors in the set of buffer descriptors is indicative of the amount of free space in the data buffer. A communications controller determines whether the data buffer is subject to overflowing by determining when the number of free buffer descriptors moves below a threshold level (a watermark). The communications controller sends a request to the transmitting device to stop transmitting data in response to determining that the data buffer is possibly subject to an overflow condition, indicating that the data buffer is nearly full.

Abstract: A device for controlling data communication flow to a data buffer of an integrated circuit is disclosed. The device receives data communicated from a transmitting device. The received data is placed in a data buffer in memory. The data buffer is defined by a set of buffer descriptors, whereby a number of free buffer descriptors in the set of buffer descriptors is indicative of the amount of free space in the data buffer. A communications controller determines whether the data buffer is subject to overflowing by determining when the number of free buffer descriptors moves below a threshold level (a watermark). The communications controller sends a request to the transmitting device to stop transmitting data in response to determining that the data buffer is possibly subject to an overflow condition, indicating that the data buffer is nearly full.