Abstract: An automatic method of critical path prediction in a computer system used with a network model representative of a circuit. Gate delays are determined for each cell used for each of the drivers in the combinational block. Load delays are also determined for each cell used for each of the drivers in the combinational block. Estimated delays may then be determined for each path between each of the drivers in the combinational block and sinks coupled to each of the drivers in the combinational blocks. Static timing analysis on the combinational block is performed by using the gate delays, the load delays, and the estimated delays to determine estimated required times and total capacity for each primary output of the sinks of the combinational block, and to determine estimated arrival times for each primary input of the drivers of the combinational block.