Patents by Inventor Ignacio J. Perez

Ignacio J. Perez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10438332
    Abstract: Various embodiments of the present technology may comprise a method and apparatus for pixel readout. The method and apparatus may comprise a pixel array capable of reading out one or more non-rectilinear subsets of the pixel array to form a non-rectilinear primary image. The one or more non-rectilinear subsets may be selected according to a desired rectilinear output image, wherein the rectilinear output image is formed using only the one or more subsets. The primary image may then be transformed to form the rectilinear output image.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: October 8, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Airell Richard Clark, II, Timothy Brown, Ignacio J. Perez, Agustin B. Hernandez
  • Publication number: 20180336667
    Abstract: Various embodiments of the present technology may comprise a method and apparatus for pixel readout. The method and apparatus may comprise a pixel array capable of reading out one or more non-rectilinear subsets of the pixel array to form a non-rectilinear primary image. The one or more non-rectilinear subsets may be selected according to a desired rectilinear output image, wherein the rectilinear output image is formed using only the one or more subsets. The primary image may then be transformed to form the rectilinear output image.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 22, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Airell Richard CLARK, II, Timothy BROWN, Ignacio J. PEREZ, Agustin B. HERNANDEZ
  • Patent number: 6252291
    Abstract: An integrated circuit chip having a substrate with several overlaying metal layers. A lower metal layer is adjacent the substrate and an upper layer is spaced above the lower layer. The chip has circuitry including a number of circuit elements, and a number of access elements, each associated with and electrically connected to one of the circuit elements. Each access element includes first and second terminals in the lower layer, and an elongated span element in the upper layer. The span element has a first end overlaying and electrically connected to the first terminal and a second end overlaying and electrically connected to the second terminal. One of the terminals may be connected to provide power or a connection to the input or output of the associated circuit element. The chip may then be modified by severing the span element, or by connecting the span element to other circuitry on the chip to disable or enable operation of the circuit element.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: June 26, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Paul R. Woods, Ignacio J. Perez