Patents by Inventor Ignatius B. Tjandrasuwita
Ignatius B. Tjandrasuwita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9843811Abstract: A method for rotating macro-blocks of a frame of a video stream. A degree of rotation for the video stream is accessed. A macro-block of the video stream is accessed. The macro-block is rotated according to the degree of rotation. The macro-block is repositioned to a new position within the frame, wherein the new position is based on the degree of rotation.Type: GrantFiled: December 6, 2016Date of Patent: December 12, 2017Assignee: Nvidia CorporationInventors: Ignatius B. Tjandrasuwita, Harikrishna M. Reddy, Iole Moccagatta
-
Patent number: 9794593Abstract: A video decoder architecture for processing out-of-order macro-blocks of a video stream. A microcode engine receives compressed data representing macro-blocks of a frame of a video stream, wherein at least one macro-block is received out-of-order. The microcode engine is for buffering the compressed data and for ordering the macro-blocks of the frame in raster scan order. A digital video decoder receives the macro-blocks in raster scan order and is for decoding the macro-blocks.Type: GrantFiled: December 9, 2005Date of Patent: October 17, 2017Assignee: Nvidia CorporationInventors: Iole Moccagatta, Ignatius B. Tjandrasuwita, Harikrishna M. Reddy
-
Publication number: 20170237992Abstract: A method for rotating macro-blocks of a frame of a video stream. A degree of rotation for the video stream is accessed. A macro-block of the video stream is accessed. The macro-block is rotated according to the degree of rotation. The macro-block is repositioned to a new position within the frame, wherein the new position is based on the degree of rotation.Type: ApplicationFiled: December 6, 2016Publication date: August 17, 2017Inventors: Ignatius B. Tjandrasuwita, Harikrishna M. Reddy, Iole Moccagatta
-
Patent number: 9516326Abstract: A method for rotating macro-blocks of a frame of a video stream. A degree of rotation for the video stream is accessed. A macro-block of the video stream is accessed. The macro-block is rotated according to the degree of rotation. The macro-block is repositioned to a new position within the frame, wherein the new position is based on the degree of rotation.Type: GrantFiled: December 9, 2005Date of Patent: December 6, 2016Assignee: NVIDIA CorporationInventors: Ignatius B. Tjandrasuwita, Harikrishna M. Reddy, Iole Moccagatta
-
Patent number: 9210437Abstract: A hardware multi-stream multi-standard video decoder device. A command parser accesses a plurality of video streams, identifies a video encoding standard used for encoding video streams of the plurality of video streams, and interleaves portions of the plurality of video streams. A plurality of hardware decoding blocks perform operations associated with decoding the plurality of video streams, wherein different subsets of the plurality of hardware decoding blocks are for decoding video streams encoded using different video encoding standards, such that interleaved video streams are decoded by activating subsets of the plurality of hardware decoding blocks for use in decoding the plurality of video streams. A plurality of register sets store parameters associated with the plurality of video streams.Type: GrantFiled: December 9, 2005Date of Patent: December 8, 2015Assignee: NVIDIA CORPORATIONInventors: Harikrishna M. Reddy, Ignatius B. Tjandrasuwita, Iole Moccagatta
-
Patent number: 9204158Abstract: A hardware multi-standard video decoder device. A command parser accesses a video stream and identifies a video encoding standard used for encoding the video stream. A plurality of hardware decoding blocks perform operations associated with decoding the video stream, wherein different subsets of the plurality of hardware decoding blocks are for decoding video streams encoded using different video encoding standards.Type: GrantFiled: December 9, 2005Date of Patent: December 1, 2015Assignee: NVIDIA CORPORATIONInventors: Ignatius B. Tjandrasuwita, Harikrishna M. Reddy, Iole Moccagatta
-
Patent number: 8768160Abstract: A flicker band automated detection system and method are presented. In one embodiment an incidental motion mitigation exposure setting method includes receiving image input information; performing a motion mitigating flicker band automatic detection process; and implementing exposure settings based upon results of the motion mitigating flicker band automatic detection process. The auto flicker band detection process includes performing a motion mitigating process on an illumination intensity indication. Content impacts on an the motion mitigated illumination intensity indication are minimized. The motion mitigated illumination intensity indication is binarized. A correlation of the motion mitigated illumination intensity and a reference illumination intensity frequency is established.Type: GrantFiled: December 30, 2009Date of Patent: July 1, 2014Assignee: Nvidia CorporationInventors: Shang Hung Lin, Hu He, Ignatius B. Tjandrasuwita
-
Patent number: 8737832Abstract: A flicker band automated detection system and method are presented. In one embodiment an incidental motion mitigation exposure setting method includes receiving image input information; performing a motion mitigating flicker band automatic detection process; and implementing exposure settings based upon results of the motion mitigating flicker band automatic detection process. The auto flicker band detection process includes performing a motion mitigating process on an illumination intensity indication. Content impacts on an the motion mitigated illumination intensity indication are minimized. The motion mitigated illumination intensity indication is binarized. A correlation of the motion mitigated illumination intensity and a reference illumination intensity frequency is established.Type: GrantFiled: February 9, 2007Date of Patent: May 27, 2014Assignee: NVIDIA CorporationInventors: Shang-Hung Lin, Hu He, Ignatius B. Tjandrasuwita
-
Patent number: 8705630Abstract: Described are methods and systems for processing data. A motion estimator uses a block of an input frame of video data and a block of a reference frame of video data to generate motion vectors according to a first encoding scheme. A motion compensator produces half pel motion vectors from the motion vectors according to a second encoding scheme that is different from the first encoding scheme.Type: GrantFiled: December 8, 2006Date of Patent: April 22, 2014Assignee: NVIDIA CorporationInventors: Derek Pappas, Atul Garg, Shankar Moni, Harikrishna M. Reddy, Matthew R. Longnecker, Christopher L. Mills, Ignatius B. Tjandrasuwita
-
Patent number: 8437405Abstract: The present invention includes a method and system for encoding video data by accessing a picture to be encoded, wherein the picture comprises a plurality of macro-blocks. A plurality of programmable counters are associated with each macro-block to be encoded. A counter associated with a macro-block of the plurality of macro-blocks is accessed and a value of the counter is determined. The method further includes determining whether to encode the macro-block as an Intra or non-Intra based on the value of the counter. If the macro-block is encoded as Intra, its counter is reset. If the macro-block is encoded as non-Intra, its counter value is updated. The counter value may be reset with a random number. Counters can be programmed such that a region of interest is defined for updating associated macro-blocks with greater frequency.Type: GrantFiled: December 8, 2004Date of Patent: May 7, 2013Assignee: Nvidia CorporationInventors: Iole Moccagatta, Atul Garg, Shankar Moni, Dipankar Talukdar, Ignatius B. Tjandrasuwita, Sandeep Shyamsukha
-
Patent number: 8355449Abstract: The present invention includes a method and system for encoding video data by accessing a picture to be encoded, wherein the picture comprises a plurality of macro-blocks. A plurality of programmable counters are associated with each macro-block to be encoded. A counter associated with a macro-block of the plurality of macro-blocks is accessed and a value of the counter is determined. The method further includes determining whether to encode the macro-block as an Intra or non-Intra based on the value of the counter. If the macro-block is encoded as Intra, its counter is reset. If the macro-block is encoded as non-Intra, its counter value is updated. The counter value may be reset with a random number. Counters can be programmed such that a region of interest is defined for updating associated macro-blocks with greater frequency.Type: GrantFiled: December 30, 2009Date of Patent: January 15, 2013Assignee: Nvidia CorporationInventors: Iole Moccagatta, Atul Garg, Shankar Moni, Dipankar Talukdar, Ignatius B. Tjandrasuwita, Sandeep Shyamsukha
-
Patent number: 7747095Abstract: Methods and systems for compressing an image are described. A plurality of transformed and quantized values associated with a block of image data is accessed. The block corresponds to a position within the image. A count of the number of bits encoded during run-length encoding of the block is made. Run-length encoding of the block is concluded should the count reach a limit.Type: GrantFiled: October 8, 2004Date of Patent: June 29, 2010Assignee: NVIDIA CorporationInventors: Ignatius B. Tjandrasuwita, Lefan Zhong
-
Publication number: 20100128788Abstract: Embodiments of the present invention include a method and system for encoding video data comprising accessing a picture to be encoded, wherein the picture comprises a plurality of macro-blocks. A plurality of programmable counters is associated with each macro-block to be encoded. A counter associated with a macro-block of the plurality of macro-blocks is accessed and a value of the counter is determined. The method further includes determining whether to encode the macro-block as an Intra or non-Intra based on the value of the counter. If the macro-block is encoded as Intra, its counter is reset. If the macro-block is encoded as non-Intra, its counter value is updated. The counter value may be reset with a random number. Counters can be programmed such that a region of interest is defined for updating associated macro-blocks with greater frequency.Type: ApplicationFiled: December 30, 2009Publication date: May 27, 2010Applicant: NVIDIA CORPORATIONInventors: Iole Moccagatta, Atul Garg, Shankar Moni, Dipankar Talukdar, Ignatius B. Tjandrasuwita, Sandeep Shyamsukha
-
Publication number: 20100103310Abstract: A flicker band automated detection system and method are presented. In one embodiment an incidental motion mitigation exposure setting method includes receiving image input information; performing a motion mitigating flicker band automatic detection process; and implementing exposure settings based upon results of the motion mitigating flicker band automatic detection process. The auto flicker band detection process includes performing a motion mitigating process on an illumination intensity indication. Content impacts on an the motion mitigated illumination intensity indication are minimized. The motion mitigated illumination intensity indication is binarized. A correlation of the motion mitigated illumination intensity and a reference illumination intensity frequency is established.Type: ApplicationFiled: December 30, 2009Publication date: April 29, 2010Applicant: NVIDIA CORPORATIONInventors: Shang-Hung Lin, Hu He, Ignatius B. Tjandrasuwita
-
Patent number: 7286066Abstract: Described are methods and systems for variable length decoding. A first execution unit executes a first single instruction that optionally reverses the order of bits in an encoded bitstream. A second execution unit executes a second single instruction that extracts a specified number of bits from the bitstream produced by the first execution unit. A third execution unit executes a third single instruction that identifies a number of consecutive zero bit values at the head of the bitstream produced by the first execution unit. The outputs of the first, second and third execution units are used in a process that decodes the encoded bitstream.Type: GrantFiled: December 16, 2005Date of Patent: October 23, 2007Assignee: Nvidia CorporationInventors: Yiu Cheong Ho, Hideo Ohira, Ignatius B. Tjandrasuwita, Prahlad R. Venkatapuram
-
Publication number: 20070189390Abstract: Described are methods and systems for processing data. A motion estimator uses a block of an input frame of video data and a block of a reference frame of video data to generate motion vectors according to a first encoding scheme. A motion compensator produces half pel motion vectors from the motion vectors according to a second encoding scheme that is different from the first encoding scheme.Type: ApplicationFiled: December 8, 2006Publication date: August 16, 2007Inventors: Derek Pappas, Atul Garg, Shankar Moni, Harikrishna M. Reddy, Matthew R. Longnecker, Christopher L. Mills, Ignatius B. Tjandrasuwita
-
Patent number: 6760035Abstract: A method to perform image transformations that are simplistic, conducive to miniaturization, and inexpensive to implement is provided. Transformations of an image stored in system memory are carried out by copying the image data, transforming the image data to a selected orientation, and outputting the transformed image for display, printing, or others. Throughout the transformation process, the image stored in system memory remains unchanged in the original orientation (T0-normal transformation). The transformation process is carried out by accessing in predetermined orders/sequences the image data copied from system memory to a frame buffer that is made up of N memory modules and arranged such that image data are stored serially with the image scan lines running the length of the frame buffer like that of a traditional frame buffer but with each memory module capable of being individually accessed.Type: GrantFiled: November 19, 2001Date of Patent: July 6, 2004Assignee: NViDiA CorporationInventor: Ignatius B. Tjandrasuwita
-
Publication number: 20030095124Abstract: A method to perform image transformations that are simplistic, conducive to miniaturization, and inexpensive to implement is provided. Transformations of an image stored in system memory are carried out by copying the image data, transforming the image data to a selected orientation, and outputting the transformed image for display, printing, or others. Throughout the transformation process, the image stored in system memory remains unchanged in the original orientation (T0-normal transformation). The transformation process is carried out by accessing in predetermined orders/sequences the image data copied from system memory to a frame buffer that is made up of N memory modules and arranged such that image data are stored serially with the image scan lines running the length of the frame buffer like that of a traditional frame buffer but with each memory module capable of being individually accessed.Type: ApplicationFiled: November 19, 2001Publication date: May 22, 2003Inventor: Ignatius B. Tjandrasuwita
-
Patent number: 6198469Abstract: A apparatus to generate gray scale shading data in response to input color data that is cost efficient and programmable is presented. The present invention allows up to 16 brightness-levels to be generated per color (e.g., Red, Green, and Blue). Under the present invention, each color pixel can be programmed to have one of the 16 brightness-level waveforms stored in a memory by dynamically changing a number of variables such as pixel color offsets, frame offset, column offset, row offset, pixel mapping data, etc. An accessing waveform index is generated from the above variables which is then used to select a brightness-level waveform from the memory. The brightness-level waveforms stored in the memory are also programmable.Type: GrantFiled: July 1, 1998Date of Patent: March 6, 2001Inventor: Ignatius B. Tjandrasuwita
-
Patent number: RE37069Abstract: The present invention relates to An apparatus for converting cathode ray tube (CRT) data to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and lower panel. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates one panel refresh frame four panel refresh frames. Through the use of this system, An increased number of gray level patterns can be provided, thereby increasing image resolution and quality.Type: GrantFiled: August 29, 1995Date of Patent: February 27, 2001Assignee: Chips & Technologies, LLCInventors: Ignatius B. Tjandrasuwita, James E. Margeson, III