Abstract: A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number which establishes a de-serialization level for frequency reduction or phase shifting. An output provide an output data stream at the desired output frequency.

Abstract: The present invention is directed to a method and apparatus for mapping a customer memory onto a plurality of physical memories.

Abstract: A method of global simplification of a netlist for an integrated circuit includes steps for generating a variable set representative of the inputs and outputs of logic elements in the netlist, re-ordering the inputs and corresponding outputs of the logic elements in the variable set, generating a key set representative of the inputs of the logic elements that are connected to the outputs, assigning names in the variable set that are representative of equivalent outputs having two or fewer essential variables to the same variable name, inserting names in the variable set representative of outputs having more than two essential variables, and assigning a value to each of the outputs having two or fewer essential variables.

Abstract: A Gaussian noise is simulated by discrete analogue ri,j. A first parameter &agr; and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on &agr;, i and j. The discrete analogue ri,j is based on a respective si,j.

Abstract: The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the representation is decomposed into a combination of instances. An instance is a component logic circuit of a general logic circuit. There are pre-created tech-libraries for the instances. For example, a pre-created tech-library is created by categorizing tech-descriptions for primitive physical circuits based on a negation index. Thus, tech-descriptions for a circuit for realizing a representation are calculated from a combination of elements of the pre-created tech-libraries. Each calculated tech-description is compared with each existing element of a tech-library for the logic function. When a calculated tech-description has at least one marked parameter better or smaller than that of all existing elements of the tech-library for the logic function, the calculated tech-description is added to the tech-library.

Abstract: A method of global simplification of a netlist for an integrated circuit includes steps for generating a variable set representative of the inputs and outputs of logic elements in the netlist, re-ordering the inputs and corresponding outputs of the logic elements in the variable set, generating a key set representative of the inputs of the logic elements that are connected to the outputs, assigning names in the variable set that are representative of equivalent outputs having two or fewer essential variables to the same variable name, inserting names in the variable set representative of outputs having more than two essential variables, and assigning a value to each of the outputs having two or fewer essential variables.

Abstract: Apparatus and process identifies a maximum or minimum value among a plurality of binary values on a plurality of a-bit wide wires in an integrated circuit module. An N-bit vector K is calculated based on n most significant bits of all a-bit binary signals, where N=2n. M N-bit vectors K—0, . . . ,K_(M−1) are calculated based on the n most significant and the m least significant bits of all a-bit binary signals, where M is at least 2m−1. A table is constructed from vectors K—0, . . . ,K(M−1) to create table vectors. A table vector is selected based on vector K, is used to derive a vector P, which in turn is used to select another table vector. The minimum or maximum binary value is identified from the two selected table vectors.

Abstract: A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells, partitioning the set of memory cells into segments, constructing a first clock tree having a first root vertex with a corresponding initial skew for each of the segments, constructing a second clock tree having a second root vertex with a corresponding initial skew for the set of non-memory cells, delay balancing the first root vertex and the second vertex clock tree, and inserting a clock buffer at a midpoint between the first root vertex and the second root vertex.

Abstract: The specification discloses a for reduction of net delays and insertion of buffers in a logic tree having a root and a plurality of leaves. The steps of the method include inserting a plurality of auxiliary nodes into the, defining discrete, approximate scales for delay, load, and ramp time, constructing a set of buffers chains for later insertion into the net tree, determining for each node on the tree a tradeoff function relating ramp time, departure time and load at the node, for each node, removing combinations of the tradeoff functions and the buffer chains, which when inserted into the tradeoff function, lead to a ramp time which exceeds a predetermined maximum allowable ramp time, for each node, using the tradeoff function to determine a minimum delay to insert, and inserting the buffer chain corresponding to the minimum delay as determined by the tradeoff function.